Lines Matching +full:0 +full:x0c440000
62 #clock-cells = <0>;
68 #clock-cells = <0>;
74 #size-cells = <0>;
76 CPU0: cpu@0 {
79 reg = <0x0 0x0>;
80 clocks = <&cpufreq_hw 0>;
91 qcom,freq-domain = <&cpufreq_hw 0>;
108 reg = <0x0 0x100>;
109 clocks = <&cpufreq_hw 0>;
120 qcom,freq-domain = <&cpufreq_hw 0>;
132 reg = <0x0 0x200>;
133 clocks = <&cpufreq_hw 0>;
144 qcom,freq-domain = <&cpufreq_hw 0>;
156 reg = <0x0 0x300>;
157 clocks = <&cpufreq_hw 0>;
168 qcom,freq-domain = <&cpufreq_hw 0>;
180 reg = <0x0 0x400>;
181 clocks = <&cpufreq_hw 0>;
192 qcom,freq-domain = <&cpufreq_hw 0>;
204 reg = <0x0 0x500>;
205 clocks = <&cpufreq_hw 0>;
216 qcom,freq-domain = <&cpufreq_hw 0>;
228 reg = <0x0 0x600>;
252 reg = <0x0 0x700>;
312 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
315 arm,psci-suspend-param = <0x40000003>;
322 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
325 arm,psci-suspend-param = <0x40000004>;
332 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
335 arm,psci-suspend-param = <0x40000003>;
345 arm,psci-suspend-param = <0x40000004>;
354 CLUSTER_SLEEP_PC: cluster-sleep-0 {
357 arm,psci-suspend-param = <0x41000044>;
366 arm,psci-suspend-param = <0x41001244>;
375 arm,psci-suspend-param = <0x4100b244>;
392 reg = <0 0x80000000 0 0>;
583 #power-domain-cells = <0>;
589 #power-domain-cells = <0>;
595 #power-domain-cells = <0>;
601 #power-domain-cells = <0>;
607 #power-domain-cells = <0>;
613 #power-domain-cells = <0>;
619 #power-domain-cells = <0>;
625 #power-domain-cells = <0>;
631 #power-domain-cells = <0>;
644 reg = <0x0 0x80000000 0x0 0x600000>;
649 reg = <0x0 0x80600000 0x0 0x200000>;
654 reg = <0x0 0x80800000 0x0 0x20000>;
659 reg = <0x0 0x80820000 0x0 0x20000>;
665 reg = <0x0 0x808ff000 0x0 0x1000>;
670 reg = <0x0 0x80900000 0x0 0x200000>;
675 reg = <0x0 0x80b00000 0x0 0x3900000>;
680 reg = <0 0x8b700000 0 0x10000>;
686 reg = <0x0 0x94600000 0x0 0x200000>;
708 qcom,local-pid = <0>;
732 qcom,local-pid = <0>;
753 qcom,local-pid = <0>;
779 soc: soc@0 {
782 ranges = <0 0 0 0 0x10 0>;
783 dma-ranges = <0 0 0 0 0x10 0>;
788 reg = <0 0x00100000 0 0x1f0000>;
801 reg = <0 0x00784000 0 0x7a0>,
802 <0 0x00780000 0 0x7a0>,
803 <0 0x00782000 0 0x100>,
804 <0 0x00786000 0 0x1fff>;
812 reg = <0x25b 0x1>;
817 reg = <0x1d2 0x2>;
824 reg = <0 0x007c4000 0 0x1000>,
825 <0 0x007c5000 0 0x1000>;
828 iommus = <&apps_smmu 0x60 0x0>;
837 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
838 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
861 opp-avg-kBps = <100000 0>;
868 opp-avg-kBps = <390000 0>;
875 reg = <0 0x008c0000 0 0x6000>;
882 iommus = <&apps_smmu 0x43 0x0>;
887 reg = <0 0x00880000 0 0x4000>;
891 pinctrl-0 = <&qup_i2c0_default>;
894 #size-cells = <0>;
895 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
896 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
897 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
907 reg = <0 0x00880000 0 0x4000>;
911 pinctrl-0 = <&qup_spi0_spi>, <&qup_spi0_cs>;
914 #size-cells = <0>;
917 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
925 reg = <0 0x00880000 0 0x4000>;
929 pinctrl-0 = <&qup_uart0_default>;
933 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
941 reg = <0 0x00884000 0 0x4000>;
945 pinctrl-0 = <&qup_i2c1_default>;
948 #size-cells = <0>;
949 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
950 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
951 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
961 reg = <0 0x00884000 0 0x4000>;
965 pinctrl-0 = <&qup_spi1_spi>, <&qup_spi1_cs>;
968 #size-cells = <0>;
971 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
979 reg = <0 0x00884000 0 0x4000>;
983 pinctrl-0 = <&qup_uart1_default>;
987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
995 reg = <0 0x00888000 0 0x4000>;
999 pinctrl-0 = <&qup_i2c2_default>;
1002 #size-cells = <0>;
1003 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1004 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1005 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1015 reg = <0 0x00888000 0 0x4000>;
1019 pinctrl-0 = <&qup_uart2_default>;
1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1031 reg = <0 0x0088c000 0 0x4000>;
1035 pinctrl-0 = <&qup_i2c3_default>;
1038 #size-cells = <0>;
1039 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1040 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1041 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1051 reg = <0 0x0088c000 0 0x4000>;
1055 pinctrl-0 = <&qup_spi3_spi>, <&qup_spi3_cs>;
1058 #size-cells = <0>;
1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1069 reg = <0 0x0088c000 0 0x4000>;
1073 pinctrl-0 = <&qup_uart3_default>;
1077 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1078 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1085 reg = <0 0x00890000 0 0x4000>;
1089 pinctrl-0 = <&qup_i2c4_default>;
1092 #size-cells = <0>;
1093 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1094 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1095 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1105 reg = <0 0x00890000 0 0x4000>;
1109 pinctrl-0 = <&qup_uart4_default>;
1113 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1114 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1121 reg = <0 0x00894000 0 0x4000>;
1125 pinctrl-0 = <&qup_i2c5_default>;
1128 #size-cells = <0>;
1129 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1130 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1131 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1141 reg = <0 0x00894000 0 0x4000>;
1145 pinctrl-0 = <&qup_spi5_spi>, <&qup_spi5_cs>;
1148 #size-cells = <0>;
1151 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1152 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1159 reg = <0 0x00894000 0 0x4000>;
1163 pinctrl-0 = <&qup_uart5_default>;
1167 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1168 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1176 reg = <0 0x00ac0000 0 0x6000>;
1183 iommus = <&apps_smmu 0x4c3 0x0>;
1188 reg = <0 0x00a80000 0 0x4000>;
1192 pinctrl-0 = <&qup_i2c6_default>;
1195 #size-cells = <0>;
1196 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1197 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1198 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1208 reg = <0 0x00a80000 0 0x4000>;
1212 pinctrl-0 = <&qup_spi6_spi>, <&qup_spi6_cs>;
1215 #size-cells = <0>;
1218 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1226 reg = <0 0x00a80000 0 0x4000>;
1230 pinctrl-0 = <&qup_uart6_default>;
1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1242 reg = <0 0x00a84000 0 0x4000>;
1246 pinctrl-0 = <&qup_i2c7_default>;
1249 #size-cells = <0>;
1250 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1251 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1252 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1262 reg = <0 0x00a84000 0 0x4000>;
1266 pinctrl-0 = <&qup_uart7_default>;
1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1278 reg = <0 0x00a88000 0 0x4000>;
1282 pinctrl-0 = <&qup_i2c8_default>;
1285 #size-cells = <0>;
1286 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1287 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1288 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1298 reg = <0 0x00a88000 0 0x4000>;
1302 pinctrl-0 = <&qup_spi8_spi>, <&qup_spi8_cs>;
1305 #size-cells = <0>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1316 reg = <0 0x00a88000 0 0x4000>;
1320 pinctrl-0 = <&qup_uart8_default>;
1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1332 reg = <0 0x00a8c000 0 0x4000>;
1336 pinctrl-0 = <&qup_i2c9_default>;
1339 #size-cells = <0>;
1340 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1341 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1342 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1352 reg = <0 0x00a8c000 0 0x4000>;
1356 pinctrl-0 = <&qup_uart9_default>;
1360 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1361 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1368 reg = <0 0x00a90000 0 0x4000>;
1372 pinctrl-0 = <&qup_i2c10_default>;
1375 #size-cells = <0>;
1376 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1377 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1378 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1388 reg = <0 0x00a90000 0 0x4000>;
1392 pinctrl-0 = <&qup_spi10_spi>, <&qup_spi10_cs>;
1395 #size-cells = <0>;
1398 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1399 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1406 reg = <0 0x00a90000 0 0x4000>;
1410 pinctrl-0 = <&qup_uart10_default>;
1414 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1415 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1422 reg = <0 0x00a94000 0 0x4000>;
1426 pinctrl-0 = <&qup_i2c11_default>;
1429 #size-cells = <0>;
1430 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1431 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1432 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1442 reg = <0 0x00a94000 0 0x4000>;
1446 pinctrl-0 = <&qup_spi11_spi>, <&qup_spi11_cs>;
1449 #size-cells = <0>;
1452 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1453 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1460 reg = <0 0x00a94000 0 0x4000>;
1464 pinctrl-0 = <&qup_uart11_default>;
1468 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1469 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1477 reg = <0 0x01500000 0 0x28000>;
1484 reg = <0 0x01620000 0 0x17080>;
1491 reg = <0 0x01638000 0 0x1000>;
1498 reg = <0 0x01650000 0 0x1000>;
1505 reg = <0 0x016e0000 0 0x15080>;
1512 reg = <0 0x01705000 0 0x9000>;
1519 reg = <0 0x0170e000 0 0x6000>;
1526 reg = <0 0x01740000 0 0x1c100>;
1534 iommus = <&apps_smmu 0x440 0x0>,
1535 <&apps_smmu 0x442 0x0>;
1536 reg = <0 0x01e40000 0 0x7000>,
1537 <0 0x01e47000 0 0x2000>,
1538 <0 0x01e04000 0 0x2c000>;
1545 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1555 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1556 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1557 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1564 qcom,smem-states = <&ipa_smp2p_out 0>,
1574 reg = <0 0x01f40000 0 0x20000>;
1580 reg = <0 0x01f60000 0 0x20000>;
1585 reg = <0 0x01fc0000 0 0x40000>;
1590 reg = <0 0x03500000 0 0x300000>,
1591 <0 0x03900000 0 0x300000>,
1592 <0 0x03d00000 0 0x300000>;
1599 gpio-ranges = <&tlmm 0 0 120>;
2049 reg = <0 0x04080000 0 0x4040>;
2052 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2072 qcom,smem-states = <&modem_smp2p_out 0>;
2087 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2088 <0 0x05061000 0 0x800>;
2091 iommus = <&adreno_smmu 0>;
2100 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2110 opp-supported-hw = <0x04>;
2117 opp-supported-hw = <0x07>;
2124 opp-supported-hw = <0x07>;
2131 opp-supported-hw = <0x07>;
2138 opp-supported-hw = <0x07>;
2145 opp-supported-hw = <0x07>;
2152 opp-supported-hw = <0x07>;
2159 opp-supported-hw = <0x07>;
2166 reg = <0 0x05040000 0 0x10000>;
2189 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2190 <0 0x0b490000 0 0x10000>;
2217 reg = <0 0x05090000 0 0x9000>;
2231 reg = <0x0 0x010a2000 0x0 0x1000>,
2232 <0x0 0x010ae000 0x0 0x2000>;
2237 reg = <0 0x06002000 0 0x1000>,
2238 <0 0x16280000 0 0x180000>;
2255 reg = <0 0x06041000 0 0x1000>;
2270 #size-cells = <0>;
2283 reg = <0 0x06042000 0 0x1000>;
2298 #size-cells = <0>;
2311 reg = <0 0x06045000 0 0x1000>;
2326 #size-cells = <0>;
2328 port@0 {
2329 reg = <0>;
2346 reg = <0 0x06046000 0 0x1000>;
2370 reg = <0 0x06048000 0 0x1000>;
2371 iommus = <&apps_smmu 0x04a0 0x20>;
2388 reg = <0 0x06b04000 0 0x1000>;
2403 #size-cells = <0>;
2416 reg = <0 0x06b05000 0 0x1000>;
2440 reg = <0 0x06b06000 0 0x1000>;
2465 reg = <0 0x07040000 0 0x1000>;
2485 reg = <0 0x07140000 0 0x1000>;
2505 reg = <0 0x07240000 0 0x1000>;
2525 reg = <0 0x07340000 0 0x1000>;
2545 reg = <0 0x07440000 0 0x1000>;
2565 reg = <0 0x07540000 0 0x1000>;
2585 reg = <0 0x07640000 0 0x1000>;
2605 reg = <0 0x07740000 0 0x1000>;
2625 reg = <0 0x07800000 0 0x1000>;
2640 #size-cells = <0>;
2642 port@0 {
2643 reg = <0>;
2702 reg = <0 0x07810000 0 0x1000>;
2726 reg = <0 0x08804000 0 0x1000>;
2728 iommus = <&apps_smmu 0x80 0>;
2738 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2739 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2755 opp-avg-kBps = <100000 0>;
2762 opp-avg-kBps = <200000 0>;
2769 reg = <0 0x088dc000 0 0x600>;
2770 iommus = <&apps_smmu 0x20 0x0>;
2772 #size-cells = <0>;
2777 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2778 &config_noc SLAVE_QSPI_0 0>;
2787 reg = <0 0x088e3000 0 0x400>;
2789 #phy-cells = <0>;
2800 reg = <0 0x088e9000 0 0x18c>,
2801 <0 0x088e8000 0 0x3c>,
2802 <0 0x088ea000 0 0x18c>;
2819 reg = <0 0x088e9200 0 0x128>,
2820 <0 0x088e9400 0 0x200>,
2821 <0 0x088e9c00 0 0x218>,
2822 <0 0x088e9600 0 0x128>,
2823 <0 0x088e9800 0 0x200>,
2824 <0 0x088e9a00 0 0x18>;
2825 #clock-cells = <0>;
2826 #phy-cells = <0>;
2833 reg = <0 0x088ea200 0 0x200>,
2834 <0 0x088ea400 0 0x200>,
2835 <0 0x088eaa00 0 0x200>,
2836 <0 0x088ea600 0 0x200>,
2837 <0 0x088ea800 0 0x200>;
2839 #phy-cells = <0>;
2845 reg = <0 0x090b6300 0 0x600>;
2855 opp-0 {
2883 reg = <0 0x090cd000 0 0x1000>;
2893 opp-0 {
2929 reg = <0 0x09160000 0 0x03200>;
2936 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2943 reg = <0 0x09680000 0 0x3e200>;
2950 reg = <0 0x09990000 0 0x1600>;
2957 reg = <0 0x0a6f8800 0 0x400>;
2991 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2992 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2999 reg = <0 0x0a600000 0 0xe000>;
3001 iommus = <&apps_smmu 0x540 0>;
3012 reg = <0 0x0aa00000 0 0xff000>;
3026 iommus = <&apps_smmu 0x0c00 0x60>;
3028 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
3029 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
3072 reg = <0 0x0ab00000 0 0x10000>;
3082 reg = <0 0x0ac00000 0 0x1000>;
3089 reg = <0 0x0ad00000 0 0x10000>;
3101 reg = <0 0x0ae00000 0 0x1000>;
3115 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
3118 iommus = <&apps_smmu 0x800 0x2>;
3128 reg = <0 0x0ae01000 0 0x8f000>,
3129 <0 0x0aeb0000 0 0x2008>;
3150 interrupts = <0>;
3154 #size-cells = <0>;
3156 port@0 {
3157 reg = <0>;
3199 reg = <0 0x0ae94000 0 0x400>;
3219 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
3227 #size-cells = <0>;
3233 #size-cells = <0>;
3235 port@0 {
3236 reg = <0>;
3271 reg = <0 0x0ae94400 0 0x200>,
3272 <0 0x0ae94600 0 0x280>,
3273 <0 0x0ae94a00 0 0x1e0>;
3279 #phy-cells = <0>;
3292 reg = <0 0x0ae90000 0 0x200>,
3293 <0 0x0ae90200 0 0x200>,
3294 <0 0x0ae90400 0 0xc00>,
3295 <0 0x0ae91000 0 0x400>,
3296 <0 0x0ae91400 0 0x400>;
3310 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3317 #sound-dai-cells = <0>;
3321 #size-cells = <0>;
3322 port@0 {
3323 reg = <0>;
3363 reg = <0 0x0af00000 0 0x200000>;
3366 <&mdss_dsi0_phy 0>,
3368 <&dp_phy 0>,
3383 reg = <0 0x0b220000 0 0x30000>;
3384 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3392 reg = <0 0x0b2e0000 0 0x20000>;
3398 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3399 <0 0x0c222000 0 0x1ff>; /* SROT */
3409 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3410 <0 0x0c223000 0 0x1ff>; /* SROT */
3420 reg = <0 0x0c2a0000 0 0x31000>;
3426 reg = <0 0x0c300000 0 0x400>;
3428 mboxes = <&apss_shared 0>;
3430 #clock-cells = <0>;
3435 reg = <0 0x0c3f0000 0 0x400>;
3440 reg = <0 0x0c440000 0 0x1100>,
3441 <0 0x0c600000 0 0x2000000>,
3442 <0 0x0e600000 0 0x100000>,
3443 <0 0x0e700000 0 0xa0000>,
3444 <0 0x0c40a000 0 0x26000>;
3448 qcom,ee = <0>;
3449 qcom,channel = <0>;
3451 #size-cells = <0>;
3458 reg = <0 0x146aa000 0 0x2000>;
3463 ranges = <0 0 0x146aa000 0x2000>;
3467 reg = <0x94c 0xc8>;
3473 reg = <0 0x15000000 0 0x100000>;
3566 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3567 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3574 reg = <0 0x17a40000 0 0x20000>;
3582 reg = <0 0x17c00000 0 0x10000>;
3588 reg = <0 0x17c10000 0 0x1000>;
3590 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3596 ranges = <0 0 0 0x20000000>;
3598 reg = <0 0x17c20000 0 0x1000>;
3601 frame-number = <0>;
3604 reg = <0x17c21000 0x1000>,
3605 <0x17c22000 0x1000>;
3611 reg = <0x17c23000 0x1000>;
3618 reg = <0x17c25000 0x1000>;
3625 reg = <0x17c27000 0x1000>;
3632 reg = <0x17c29000 0x1000>;
3639 reg = <0x17c2b000 0x1000>;
3646 reg = <0x17c2d000 0x1000>;
3653 reg = <0 0x18200000 0 0x10000>,
3654 <0 0x18210000 0 0x10000>,
3655 <0 0x18220000 0 0x10000>;
3656 reg-names = "drv-0", "drv-1", "drv-2";
3660 qcom,tcs-offset = <0xd00>;
3736 reg = <0 0x18321000 0 0x1400>;
3746 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3758 reg = <0 0x18800000 0 0x800000>;
3760 iommus = <&apps_smmu 0xc0 0x1>;
3781 reg = <0 0x62d00000 0 0x50000>,
3782 <0 0x62780000 0 0x30000>;
3797 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3800 iommus = <&apps_smmu 0x1020 0>,
3801 <&apps_smmu 0x1021 0>,
3802 <&apps_smmu 0x1032 0>;
3823 #size-cells = <0>;
3832 reg = <0 0x63000000 0 0x28>;
3848 polling-delay = <0>;
3897 polling-delay = <0>;
3946 polling-delay = <0>;
3995 polling-delay = <0>;
4044 polling-delay = <0>;
4093 polling-delay = <0>;
4142 polling-delay = <0>;
4183 polling-delay = <0>;
4224 polling-delay = <0>;
4265 polling-delay = <0>;
4306 polling-delay = <0>;
4308 thermal-sensors = <&tsens0 0>;
4327 polling-delay = <0>;
4347 polling-delay = <0>;
4367 polling-delay = <0>;
4395 polling-delay = <0>;
4423 polling-delay = <0>;
4425 thermal-sensors = <&tsens1 0>;
4444 polling-delay = <0>;
4465 polling-delay = <0>;
4486 polling-delay = <0>;
4507 polling-delay = <0>;
4528 polling-delay = <0>;
4549 polling-delay = <0>;
4570 polling-delay = <0>;
4591 polling-delay = <0>;
4612 polling-delay = <0>;
4637 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;