Lines Matching refs:gcc
9 #include <dt-bindings/clock/qcom,sa8775p-gcc.h>
468 gcc: clock-controller@100000 { label
469 compatible = "qcom,sa8775p-gcc";
505 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,
506 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;
519 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
540 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>;
561 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
582 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>;
603 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
622 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>;
645 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
666 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
685 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>;
700 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
723 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>;
744 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
765 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>;
786 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
807 clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>;
830 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
831 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
841 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
862 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
883 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
904 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
925 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
946 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
967 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
988 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
1009 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1030 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1051 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1072 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1091 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1110 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1111 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1121 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1142 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1163 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1184 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1205 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1226 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1245 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1262 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1283 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1303 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1320 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1341 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1362 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1383 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1402 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1419 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>;
1442 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>,
1443 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>;
1453 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1474 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>;
1498 resets = <&gcc GCC_UFS_PHY_BCR>;
1500 power-domains = <&gcc UFS_PHY_GDSC>;
1504 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
1505 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
1506 <&gcc GCC_UFS_PHY_AHB_CLK>,
1507 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
1509 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
1510 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
1511 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
1539 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
1540 <&gcc GCC_EDP_REF_CLKREF_EN>;
1542 power-domains = <&gcc UFS_PHY_GDSC>;
1555 resets = <&gcc GCC_USB2_PHY_PRIM_BCR>;
1566 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
1567 <&gcc GCC_USB_CLKREF_EN>,
1568 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
1569 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
1572 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
1573 <&gcc GCC_USB3PHY_PHY_PRIM_BCR>;
1576 power-domains = <&gcc USB30_PRIM_GDSC>;
1593 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
1594 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
1595 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
1596 <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
1597 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>;
1600 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
1601 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
1613 power-domains = <&gcc USB30_PRIM_GDSC>;
1616 resets = <&gcc GCC_USB30_PRIM_BCR>;
1640 clocks = <&gcc GCC_USB_CLKREF_EN>;
1642 resets = <&gcc GCC_USB2_PHY_SEC_BCR>;
1653 clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
1654 <&gcc GCC_USB_CLKREF_EN>,
1655 <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
1656 <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
1659 resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
1660 <&gcc GCC_USB3PHY_PHY_SEC_BCR>;
1663 power-domains = <&gcc USB30_SEC_GDSC>;
1680 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
1681 <&gcc GCC_USB30_SEC_MASTER_CLK>,
1682 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
1683 <&gcc GCC_USB30_SEC_SLEEP_CLK>,
1684 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>;
1687 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
1688 <&gcc GCC_USB30_SEC_MASTER_CLK>;
1700 power-domains = <&gcc USB30_SEC_GDSC>;
1703 resets = <&gcc GCC_USB30_SEC_BCR>;
1727 clocks = <&gcc GCC_USB_CLKREF_EN>;
1729 resets = <&gcc GCC_USB3_PHY_TERT_BCR>;
1743 clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
1744 <&gcc GCC_USB20_MASTER_CLK>,
1745 <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
1746 <&gcc GCC_USB20_SLEEP_CLK>,
1747 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
1750 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
1751 <&gcc GCC_USB20_MASTER_CLK>;
1761 power-domains = <&gcc USB20_PRIM_GDSC>;
1764 resets = <&gcc GCC_USB20_PRIM_BCR>;
1794 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
1795 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
1812 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
1813 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
1843 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
1852 clocks = <&gcc GCC_SGMI_CLKREF_EN>;
2323 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
2338 clocks = <&gcc GCC_EMAC1_AXI_CLK>,
2339 <&gcc GCC_EMAC1_SLV_AHB_CLK>,
2340 <&gcc GCC_EMAC1_PTP_CLK>,
2341 <&gcc GCC_EMAC1_PHY_AUX_CLK>;
2347 power-domains = <&gcc EMAC1_GDSC>;
2371 clocks = <&gcc GCC_EMAC0_AXI_CLK>,
2372 <&gcc GCC_EMAC0_SLV_AHB_CLK>,
2373 <&gcc GCC_EMAC0_PTP_CLK>,
2374 <&gcc GCC_EMAC0_PHY_AUX_CLK>;
2380 power-domains = <&gcc EMAC0_GDSC>;
2443 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2444 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2445 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
2446 <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
2447 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
2455 assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>;
2465 resets = <&gcc GCC_PCIE_0_BCR>;
2467 power-domains = <&gcc PCIE_0_GDSC>;
2479 clocks = <&gcc GCC_PCIE_0_AUX_CLK>,
2480 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
2481 <&gcc GCC_PCIE_CLKREF_EN>,
2482 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
2483 <&gcc GCC_PCIE_0_PIPE_CLK>,
2484 <&gcc GCC_PCIE_0_PIPEDIV2_CLK>,
2485 <&gcc GCC_PCIE_0_PHY_AUX_CLK>;
2490 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>;
2493 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
2543 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2544 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2545 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>,
2546 <&gcc GCC_PCIE_1_SLV_AXI_CLK>,
2547 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>;
2555 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>;
2565 resets = <&gcc GCC_PCIE_1_BCR>;
2567 power-domains = <&gcc PCIE_1_GDSC>;
2579 clocks = <&gcc GCC_PCIE_1_AUX_CLK>,
2580 <&gcc GCC_PCIE_1_CFG_AHB_CLK>,
2581 <&gcc GCC_PCIE_CLKREF_EN>,
2582 <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>,
2583 <&gcc GCC_PCIE_1_PIPE_CLK>,
2584 <&gcc GCC_PCIE_1_PIPEDIV2_CLK>,
2585 <&gcc GCC_PCIE_1_PHY_AUX_CLK>;
2590 assigned-clocks = <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>;
2593 resets = <&gcc GCC_PCIE_1_PHY_BCR>;