Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-qcs404.h>
316 clocks = <&gcc GCC_CDSP_CFG_AHB_CLK>;
334 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
335 <&gcc GCC_USB3_PHY_PIPE_CLK>;
337 resets = <&gcc GCC_USB3_PHY_BCR>,
338 <&gcc GCC_USB3PHY_PHY_BCR>;
348 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
349 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
351 resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
352 <&gcc GCC_USB2A_PHY_BCR>;
362 <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
363 <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
365 resets = <&gcc GCC_QUSB2_PHY_BCR>,
366 <&gcc GCC_USB2_HS_PHY_ONLY_BCR>;
553 clocks = <&gcc GCC_PRNG_AHB_CLK>;
636 * <&gcc GCC_CDSP_CFG_AHB_CLK>,
637 * <&gcc GCC_CDSP_TBU_CLK>,
638 * <&gcc GCC_BIMC_CDSP_CLK>,
651 * resets = <&gcc GCC_CDSP_RESTART>;
679 clocks = <&gcc GCC_USB30_MASTER_CLK>,
680 <&gcc GCC_SYS_NOC_USB3_CLK>,
681 <&gcc GCC_USB30_SLEEP_CLK>,
682 <&gcc GCC_USB30_MOCK_UTMI_CLK>;
684 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
685 <&gcc GCC_USB30_MASTER_CLK>;
708 clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>,
709 <&gcc GCC_PCNOC_USB2_CLK>,
710 <&gcc GCC_USB_HS_INACTIVITY_TIMERS_CLK>,
711 <&gcc GCC_USB20_MOCK_UTMI_CLK>;
713 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
714 <&gcc GCC_USB_HS_SYSTEM_CLK>;
873 gcc: clock-controller@1800000 { label
874 compatible = "qcom,gcc-qcs404";
887 assigned-clocks = <&gcc GCC_APSS_AHB_CLK_SRC>;
961 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
962 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
963 <&gcc GCC_PCIE_0_PIPE_ARES>;
982 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
983 <&gcc GCC_SDCC1_APPS_CLK>,
994 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
1005 clocks = <&gcc GCC_BLSP1_UART0_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1018 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1031 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1046 clocks = <&gcc GCC_ETH_AXI_CLK>,
1047 <&gcc GCC_ETH_SLAVE_AHB_CLK>,
1048 <&gcc GCC_ETH_PTP_CLK>,
1049 <&gcc GCC_ETH_RGMII_CLK>;
1085 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
1098 clocks = <&gcc GCC_BLSP1_QUP0_I2C_APPS_CLK>,
1099 <&gcc GCC_BLSP1_AHB_CLK>;
1112 clocks = <&gcc GCC_BLSP1_QUP0_SPI_APPS_CLK>,
1113 <&gcc GCC_BLSP1_AHB_CLK>;
1126 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
1127 <&gcc GCC_BLSP1_AHB_CLK>;
1140 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
1141 <&gcc GCC_BLSP1_AHB_CLK>;
1154 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
1155 <&gcc GCC_BLSP1_AHB_CLK>;
1168 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
1169 <&gcc GCC_BLSP1_AHB_CLK>;
1182 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
1183 <&gcc GCC_BLSP1_AHB_CLK>;
1196 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
1197 <&gcc GCC_BLSP1_AHB_CLK>;
1210 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
1211 <&gcc GCC_BLSP1_AHB_CLK>;
1224 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
1225 <&gcc GCC_BLSP1_AHB_CLK>;
1238 clocks = <&gcc GCC_BLSP2_AHB_CLK>;
1249 clocks = <&gcc GCC_BLSP2_UART0_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
1262 clocks = <&gcc GCC_BLSP2_QUP0_I2C_APPS_CLK>,
1263 <&gcc GCC_BLSP2_AHB_CLK>;
1276 clocks = <&gcc GCC_BLSP2_QUP0_SPI_APPS_CLK>,
1277 <&gcc GCC_BLSP2_AHB_CLK>;
1314 clocks = <&apcs_hfpll>, <&gcc GCC_GPLL0_AO_OUT_MAIN>;
1489 clocks = <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
1490 <&gcc GCC_PCIE_0_AUX_CLK>,
1491 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
1492 <&gcc GCC_PCIE_0_SLV_AXI_CLK>;
1495 resets = <&gcc GCC_PCIE_0_AXI_MASTER_ARES>,
1496 <&gcc GCC_PCIE_0_AXI_SLAVE_ARES>,
1497 <&gcc GCC_PCIE_0_AXI_MASTER_STICKY_ARES>,
1498 <&gcc GCC_PCIE_0_CORE_STICKY_ARES>,
1499 <&gcc GCC_PCIE_0_BCR>,
1500 <&gcc GCC_PCIE_0_AHB_ARES>;