Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/clock/qcom,gcc-msm8998.h>
6 #include <dt-bindings/clock/qcom,gpucc-msm8998.h>
7 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
8 #include <dt-bindings/clock/qcom,rpmcc.h>
9 #include <dt-bindings/power/qcom-rpmpd.h>
10 #include <dt-bindings/gpio/gpio.h>
13 interrupt-parent = <&intc>;
15 qcom,msm-id = <292 0x0>;
17 #address-cells = <2>;
18 #size-cells = <2>;
28 reserved-memory {
29 #address-cells = <2>;
30 #size-cells = <2>;
35 no-map;
40 no-map;
43 smem_mem: smem-mem@86000000 {
45 no-map;
50 no-map;
54 compatible = "qcom,rmtfs-mem";
56 no-map;
58 qcom,client-id = <1>;
64 no-map;
69 no-map;
74 no-map;
79 no-map;
84 no-map;
89 no-map;
94 no-map;
99 no-map;
104 no-map;
109 no-map;
112 mdata_mem: mpss-metadata {
113 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
115 no-map;
120 xo: xo-board {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <19200000>;
124 clock-output-names = "xo_board";
127 sleep_clk: sleep-clk {
128 compatible = "fixed-clock";
129 #clock-cells = <0>;
130 clock-frequency = <32764>;
135 #address-cells = <2>;
136 #size-cells = <0>;
142 enable-method = "psci";
143 capacity-dmips-mhz = <1024>;
144 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
145 next-level-cache = <&L2_0>;
146 L2_0: l2-cache {
148 cache-level = <2>;
149 cache-unified;
157 enable-method = "psci";
158 capacity-dmips-mhz = <1024>;
159 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
160 next-level-cache = <&L2_0>;
167 enable-method = "psci";
168 capacity-dmips-mhz = <1024>;
169 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
170 next-level-cache = <&L2_0>;
177 enable-method = "psci";
178 capacity-dmips-mhz = <1024>;
179 cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
180 next-level-cache = <&L2_0>;
187 enable-method = "psci";
188 capacity-dmips-mhz = <1536>;
189 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
190 next-level-cache = <&L2_1>;
191 L2_1: l2-cache {
193 cache-level = <2>;
194 cache-unified;
202 enable-method = "psci";
203 capacity-dmips-mhz = <1536>;
204 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
205 next-level-cache = <&L2_1>;
212 enable-method = "psci";
213 capacity-dmips-mhz = <1536>;
214 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
215 next-level-cache = <&L2_1>;
222 enable-method = "psci";
223 capacity-dmips-mhz = <1536>;
224 cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
225 next-level-cache = <&L2_1>;
228 cpu-map {
266 idle-states {
267 entry-method = "psci";
269 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
270 compatible = "arm,idle-state";
271 idle-state-name = "little-retention";
273 arm,psci-suspend-param = <0x00000002>;
274 entry-latency-us = <81>;
275 exit-latency-us = <86>;
276 min-residency-us = <504>;
279 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
280 compatible = "arm,idle-state";
281 idle-state-name = "little-power-collapse";
283 arm,psci-suspend-param = <0x40000003>;
284 entry-latency-us = <814>;
285 exit-latency-us = <4562>;
286 min-residency-us = <9183>;
287 local-timer-stop;
290 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
291 compatible = "arm,idle-state";
292 idle-state-name = "big-retention";
294 arm,psci-suspend-param = <0x00000002>;
295 entry-latency-us = <79>;
296 exit-latency-us = <82>;
297 min-residency-us = <1302>;
300 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
301 compatible = "arm,idle-state";
302 idle-state-name = "big-power-collapse";
304 arm,psci-suspend-param = <0x40000003>;
305 entry-latency-us = <724>;
306 exit-latency-us = <2027>;
307 min-residency-us = <9419>;
308 local-timer-stop;
315 compatible = "qcom,scm-msm8998", "qcom,scm";
319 dsi_opp_table: opp-table-dsi {
320 compatible = "operating-points-v2";
322 opp-131250000 {
323 opp-hz = /bits/ 64 <131250000>;
324 required-opps = <&rpmpd_opp_low_svs>;
327 opp-210000000 {
328 opp-hz = /bits/ 64 <210000000>;
329 required-opps = <&rpmpd_opp_svs>;
332 opp-312500000 {
333 opp-hz = /bits/ 64 <312500000>;
334 required-opps = <&rpmpd_opp_nom>;
339 compatible = "arm,psci-1.0";
344 compatible = "qcom,msm8998-rpm-proc", "qcom,rpm-proc";
346 glink-edge {
347 compatible = "qcom,glink-rpm";
350 qcom,rpm-msg-ram = <&rpm_msg_ram>;
353 rpm_requests: rpm-requests {
354 compatible = "qcom,rpm-msm8998";
355 qcom,glink-channels = "rpm_requests";
357 rpmcc: clock-controller {
358 compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
360 clock-names = "xo";
361 #clock-cells = <1>;
364 rpmpd: power-controller {
365 compatible = "qcom,msm8998-rpmpd";
366 #power-domain-cells = <1>;
367 operating-points-v2 = <&rpmpd_opp_table>;
369 rpmpd_opp_table: opp-table {
370 compatible = "operating-points-v2";
373 opp-level = <RPM_SMD_LEVEL_RETENTION>;
377 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
381 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
385 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
389 opp-level = <RPM_SMD_LEVEL_SVS>;
393 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
397 opp-level = <RPM_SMD_LEVEL_NOM>;
401 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
405 opp-level = <RPM_SMD_LEVEL_TURBO>;
409 opp-level = <RPM_SMD_LEVEL_BINNING>;
419 memory-region = <&smem_mem>;
423 smp2p-lpass {
431 qcom,local-pid = <0>;
432 qcom,remote-pid = <2>;
434 adsp_smp2p_out: master-kernel {
435 qcom,entry-name = "master-kernel";
436 #qcom,smem-state-cells = <1>;
439 adsp_smp2p_in: slave-kernel {
440 qcom,entry-name = "slave-kernel";
442 interrupt-controller;
443 #interrupt-cells = <2>;
447 smp2p-mpss {
452 qcom,local-pid = <0>;
453 qcom,remote-pid = <1>;
455 modem_smp2p_out: master-kernel {
456 qcom,entry-name = "master-kernel";
457 #qcom,smem-state-cells = <1>;
460 modem_smp2p_in: slave-kernel {
461 qcom,entry-name = "slave-kernel";
462 interrupt-controller;
463 #interrupt-cells = <2>;
467 smp2p-slpi {
472 qcom,local-pid = <0>;
473 qcom,remote-pid = <3>;
475 slpi_smp2p_out: master-kernel {
476 qcom,entry-name = "master-kernel";
477 #qcom,smem-state-cells = <1>;
480 slpi_smp2p_in: slave-kernel {
481 qcom,entry-name = "slave-kernel";
482 interrupt-controller;
483 #interrupt-cells = <2>;
487 thermal-zones {
488 cpu0-thermal {
489 polling-delay-passive = <250>;
490 polling-delay = <1000>;
492 thermal-sensors = <&tsens0 1>;
495 cpu0_alert0: trip-point0 {
501 cpu0_crit: cpu-crit {
509 cpu1-thermal {
510 polling-delay-passive = <250>;
511 polling-delay = <1000>;
513 thermal-sensors = <&tsens0 2>;
516 cpu1_alert0: trip-point0 {
522 cpu1_crit: cpu-crit {
530 cpu2-thermal {
531 polling-delay-passive = <250>;
532 polling-delay = <1000>;
534 thermal-sensors = <&tsens0 3>;
537 cpu2_alert0: trip-point0 {
543 cpu2_crit: cpu-crit {
551 cpu3-thermal {
552 polling-delay-passive = <250>;
553 polling-delay = <1000>;
555 thermal-sensors = <&tsens0 4>;
558 cpu3_alert0: trip-point0 {
564 cpu3_crit: cpu-crit {
572 cpu4-thermal {
573 polling-delay-passive = <250>;
574 polling-delay = <1000>;
576 thermal-sensors = <&tsens0 7>;
579 cpu4_alert0: trip-point0 {
585 cpu4_crit: cpu-crit {
593 cpu5-thermal {
594 polling-delay-passive = <250>;
595 polling-delay = <1000>;
597 thermal-sensors = <&tsens0 8>;
600 cpu5_alert0: trip-point0 {
606 cpu5_crit: cpu-crit {
614 cpu6-thermal {
615 polling-delay-passive = <250>;
616 polling-delay = <1000>;
618 thermal-sensors = <&tsens0 9>;
621 cpu6_alert0: trip-point0 {
627 cpu6_crit: cpu-crit {
635 cpu7-thermal {
636 polling-delay-passive = <250>;
637 polling-delay = <1000>;
639 thermal-sensors = <&tsens0 10>;
642 cpu7_alert0: trip-point0 {
648 cpu7_crit: cpu-crit {
656 gpu-bottom-thermal {
657 polling-delay-passive = <250>;
658 polling-delay = <1000>;
660 thermal-sensors = <&tsens0 12>;
663 gpu1_alert0: trip-point0 {
671 gpu-top-thermal {
672 polling-delay-passive = <250>;
673 polling-delay = <1000>;
675 thermal-sensors = <&tsens0 13>;
678 gpu2_alert0: trip-point0 {
686 clust0-mhm-thermal {
687 polling-delay-passive = <250>;
688 polling-delay = <1000>;
690 thermal-sensors = <&tsens0 5>;
693 cluster0_mhm_alert0: trip-point0 {
701 clust1-mhm-thermal {
702 polling-delay-passive = <250>;
703 polling-delay = <1000>;
705 thermal-sensors = <&tsens0 6>;
708 cluster1_mhm_alert0: trip-point0 {
716 cluster1-l2-thermal {
717 polling-delay-passive = <250>;
718 polling-delay = <1000>;
720 thermal-sensors = <&tsens0 11>;
723 cluster1_l2_alert0: trip-point0 {
731 modem-thermal {
732 polling-delay-passive = <250>;
733 polling-delay = <1000>;
735 thermal-sensors = <&tsens1 1>;
738 modem_alert0: trip-point0 {
746 mem-thermal {
747 polling-delay-passive = <250>;
748 polling-delay = <1000>;
750 thermal-sensors = <&tsens1 2>;
753 mem_alert0: trip-point0 {
761 wlan-thermal {
762 polling-delay-passive = <250>;
763 polling-delay = <1000>;
765 thermal-sensors = <&tsens1 3>;
768 wlan_alert0: trip-point0 {
776 q6-dsp-thermal {
777 polling-delay-passive = <250>;
778 polling-delay = <1000>;
780 thermal-sensors = <&tsens1 4>;
783 q6_dsp_alert0: trip-point0 {
791 camera-thermal {
792 polling-delay-passive = <250>;
793 polling-delay = <1000>;
795 thermal-sensors = <&tsens1 5>;
798 camera_alert0: trip-point0 {
806 multimedia-thermal {
807 polling-delay-passive = <250>;
808 polling-delay = <1000>;
810 thermal-sensors = <&tsens1 6>;
813 multimedia_alert0: trip-point0 {
823 compatible = "arm,armv8-timer";
831 #address-cells = <1>;
832 #size-cells = <1>;
834 compatible = "simple-bus";
836 gcc: clock-controller@100000 {
837 compatible = "qcom,gcc-msm8998";
838 #clock-cells = <1>;
839 #reset-cells = <1>;
840 #power-domain-cells = <1>;
843 clock-names = "xo", "sleep_clk";
848 * reside as read-only for the HLOS. If the HLOS tried to enable or disable
850 * enabled but unused during boot-up), the device will most likely decide
853 * as protected. The board dts (or a user-supplied dts) can override the
857 protected-clocks = <AGGRE2_SNOC_NORTH_AXI>,
863 compatible = "qcom,rpm-msg-ram";
868 compatible = "qcom,msm8998-qfprom", "qcom,qfprom";
870 #address-cells = <1>;
871 #size-cells = <1>;
873 qusb2_hstx_trim: hstx-trim@23a {
880 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
886 interrupt-names = "uplow", "critical";
887 #thermal-sensor-cells = <1>;
891 compatible = "qcom,msm8998-tsens", "qcom,tsens-v2";
897 interrupt-names = "uplow", "critical";
898 #thermal-sensor-cells = <1>;
902 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
904 #iommu-cells = <1>;
906 #global-interrupts = <0>;
917 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
919 #iommu-cells = <1>;
921 #global-interrupts = <0>;
936 compatible = "qcom,pcie-msm8998", "qcom,pcie-msm8996";
941 reg-names = "parf", "dbi", "elbi", "config";
943 linux,pci-domain = <0>;
944 bus-range = <0x00 0xff>;
945 #address-cells = <3>;
946 #size-cells = <2>;
947 num-lanes = <1>;
949 phy-names = "pciephy";
955 #interrupt-cells = <1>;
957 interrupt-names = "msi";
958 interrupt-map-mask = <0 0 0 0x7>;
959 interrupt-map = <0 0 0 1 &intc 0 0 135 IRQ_TYPE_LEVEL_HIGH>,
969 clock-names = "pipe", "aux", "cfg", "bus_master", "bus_slave";
971 power-domains = <&gcc PCIE_0_GDSC>;
972 iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
973 perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
977 compatible = "qcom,msm8998-qmp-pcie-phy";
979 #address-cells = <1>;
980 #size-cells = <1>;
987 clock-names = "aux", "cfg_ahb", "ref";
990 reset-names = "phy", "common";
992 vdda-phy-supply = <&vreg_l1a_0p875>;
993 vdda-pll-supply = <&vreg_l2a_1p2>;
997 #phy-cells = <0>;
1000 clock-names = "pipe0";
1001 clock-output-names = "pcie_0_pipe_clk_src";
1002 #clock-cells = <0>;
1007 compatible = "qcom,msm8998-ufshc", "qcom,ufshc", "jedec,ufs-2.0";
1011 phy-names = "ufsphy";
1012 lanes-per-direction = <2>;
1013 power-domains = <&gcc UFS_GDSC>;
1015 #reset-cells = <1>;
1017 clock-names =
1035 freq-table-hz =
1046 reset-names = "rst";
1050 compatible = "qcom,msm8998-qmp-ufs-phy";
1052 #address-cells = <1>;
1053 #size-cells = <1>;
1057 clock-names =
1064 reset-names = "ufsphy";
1073 #phy-cells = <0>;
1078 compatible = "qcom,tcsr-mutex";
1080 #hwlock-cells = <1>;
1084 compatible = "qcom,msm8998-tcsr", "syscon";
1089 compatible = "qcom,msm8998-pinctrl";
1092 gpio-ranges = <&tlmm 0 0 150>;
1093 gpio-controller;
1094 #gpio-cells = <2>;
1095 interrupt-controller;
1096 #interrupt-cells = <2>;
1098 sdc2_on: sdc2-on-state {
1099 clk-pins {
1101 drive-strength = <16>;
1102 bias-disable;
1105 cmd-pins {
1107 drive-strength = <10>;
1108 bias-pull-up;
1111 data-pins {
1113 drive-strength = <10>;
1114 bias-pull-up;
1118 sdc2_off: sdc2-off-state {
1119 clk-pins {
1121 drive-strength = <2>;
1122 bias-disable;
1125 cmd-pins {
1127 drive-strength = <2>;
1128 bias-pull-up;
1131 data-pins {
1133 drive-strength = <2>;
1134 bias-pull-up;
1138 sdc2_cd: sdc2-cd-state {
1141 bias-pull-up;
1142 drive-strength = <2>;
1145 blsp1_uart3_on: blsp1-uart3-on-state {
1146 tx-pins {
1149 drive-strength = <2>;
1150 bias-disable;
1153 rx-pins {
1156 drive-strength = <2>;
1157 bias-disable;
1160 cts-pins {
1163 drive-strength = <2>;
1164 bias-disable;
1167 rfr-pins {
1170 drive-strength = <2>;
1171 bias-disable;
1175 blsp1_i2c1_default: blsp1-i2c1-default-state {
1178 drive-strength = <2>;
1179 bias-disable;
1182 blsp1_i2c1_sleep: blsp1-i2c1-sleep-state-state {
1185 drive-strength = <2>;
1186 bias-pull-up;
1189 blsp1_i2c2_default: blsp1-i2c2-default-state {
1192 drive-strength = <2>;
1193 bias-disable;
1196 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state-state {
1199 drive-strength = <2>;
1200 bias-pull-up;
1203 blsp1_i2c3_default: blsp1-i2c3-default-state {
1206 drive-strength = <2>;
1207 bias-disable;
1210 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1213 drive-strength = <2>;
1214 bias-pull-up;
1217 blsp1_i2c4_default: blsp1-i2c4-default-state {
1220 drive-strength = <2>;
1221 bias-disable;
1224 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
1227 drive-strength = <2>;
1228 bias-pull-up;
1231 blsp1_i2c5_default: blsp1-i2c5-default-state {
1234 drive-strength = <2>;
1235 bias-disable;
1238 blsp1_i2c5_sleep: blsp1-i2c5-sleep-state {
1241 drive-strength = <2>;
1242 bias-pull-up;
1245 blsp1_i2c6_default: blsp1-i2c6-default-state {
1248 drive-strength = <2>;
1249 bias-disable;
1252 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1255 drive-strength = <2>;
1256 bias-pull-up;
1259 blsp1_spi_b_default: blsp1-spi-b-default-state {
1262 drive-strength = <6>;
1263 bias-disable;
1266 blsp1_spi1_default: blsp1-spi1-default-state {
1269 drive-strength = <6>;
1270 bias-disable;
1273 blsp1_spi2_default: blsp1-spi2-default-state {
1276 drive-strength = <6>;
1277 bias-disable;
1280 blsp1_spi3_default: blsp1-spi3-default-state {
1283 drive-strength = <6>;
1284 bias-disable;
1287 blsp1_spi4_default: blsp1-spi4-default-state {
1290 drive-strength = <6>;
1291 bias-disable;
1294 blsp1_spi5_default: blsp1-spi5-default-state {
1297 drive-strength = <6>;
1298 bias-disable;
1301 blsp1_spi6_default: blsp1-spi6-default-state {
1304 drive-strength = <6>;
1305 bias-disable;
1310 blsp2_i2c1_default: blsp2-i2c1-default-state {
1313 drive-strength = <2>;
1314 bias-disable;
1317 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1320 drive-strength = <2>;
1321 bias-pull-up;
1324 blsp2_i2c2_default: blsp2-i2c2-default-state {
1327 drive-strength = <2>;
1328 bias-disable;
1331 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1334 drive-strength = <2>;
1335 bias-pull-up;
1338 blsp2_i2c3_default: blsp2-i2c3-default-state {
1341 drive-strength = <2>;
1342 bias-disable;
1345 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1348 drive-strength = <2>;
1349 bias-pull-up;
1352 blsp2_i2c4_default: blsp2-i2c4-default-state {
1355 drive-strength = <2>;
1356 bias-disable;
1359 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
1362 drive-strength = <2>;
1363 bias-pull-up;
1366 blsp2_i2c5_default: blsp2-i2c5-default-state {
1369 drive-strength = <2>;
1370 bias-disable;
1373 blsp2_i2c5_sleep: blsp2-i2c5-sleep-state {
1376 drive-strength = <2>;
1377 bias-pull-up;
1380 blsp2_i2c6_default: blsp2-i2c6-default-state {
1383 drive-strength = <2>;
1384 bias-disable;
1387 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1390 drive-strength = <2>;
1391 bias-pull-up;
1394 blsp2_spi1_default: blsp2-spi1-default-state {
1397 drive-strength = <6>;
1398 bias-disable;
1401 blsp2_spi2_default: blsp2-spi2-default-state {
1404 drive-strength = <6>;
1405 bias-disable;
1408 blsp2_spi3_default: blsp2-spi3-default-state {
1411 drive-strength = <6>;
1412 bias-disable;
1415 blsp2_spi4_default: blsp2-spi4-default-state {
1418 drive-strength = <6>;
1419 bias-disable;
1422 blsp2_spi5_default: blsp2-spi5-default-state {
1425 drive-strength = <6>;
1426 bias-disable;
1429 blsp2_spi6_default: blsp2-spi6-default-state {
1432 drive-strength = <6>;
1433 bias-disable;
1438 compatible = "qcom,msm8998-mss-pil";
1440 reg-names = "qdsp6", "rmb";
1442 interrupts-extended =
1449 interrupt-names = "wdog", "fatal", "ready",
1450 "handover", "stop-ack",
1451 "shutdown-ack";
1461 clock-names = "iface", "bus", "mem", "gpll0_mss",
1464 qcom,smem-states = <&modem_smp2p_out 0>;
1465 qcom,smem-state-names = "stop";
1468 reset-names = "mss_restart";
1470 qcom,halt-regs = <&tcsr_regs_1 0x3000 0x5000 0x4000>;
1472 power-domains = <&rpmpd MSM8998_VDDCX>,
1474 power-domain-names = "cx", "mx";
1479 memory-region = <&mba_mem>;
1483 memory-region = <&mpss_mem>;
1487 memory-region = <&mdata_mem>;
1490 glink-edge {
1493 qcom,remote-pid = <1>;
1499 compatible = "qcom,adreno-540.1", "qcom,adreno";
1501 reg-names = "kgsl_3d0_reg_memory";
1509 clock-names = "iface",
1518 operating-points-v2 = <&gpu_opp_table>;
1519 power-domains = <&rpmpd MSM8998_VDDMX>;
1522 gpu_opp_table: opp-table {
1523 compatible = "operating-points-v2";
1524 opp-710000097 {
1525 opp-hz = /bits/ 64 <710000097>;
1526 opp-level = <RPM_SMD_LEVEL_TURBO>;
1527 opp-supported-hw = <0xff>;
1530 opp-670000048 {
1531 opp-hz = /bits/ 64 <670000048>;
1532 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
1533 opp-supported-hw = <0xff>;
1536 opp-596000097 {
1537 opp-hz = /bits/ 64 <596000097>;
1538 opp-level = <RPM_SMD_LEVEL_NOM>;
1539 opp-supported-hw = <0xff>;
1542 opp-515000097 {
1543 opp-hz = /bits/ 64 <515000097>;
1544 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
1545 opp-supported-hw = <0xff>;
1548 opp-414000000 {
1549 opp-hz = /bits/ 64 <414000000>;
1550 opp-level = <RPM_SMD_LEVEL_SVS>;
1551 opp-supported-hw = <0xff>;
1554 opp-342000000 {
1555 opp-hz = /bits/ 64 <342000000>;
1556 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
1557 opp-supported-hw = <0xff>;
1560 opp-257000000 {
1561 opp-hz = /bits/ 64 <257000000>;
1562 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
1563 opp-supported-hw = <0xff>;
1569 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
1574 clock-names = "iface", "mem", "mem_iface";
1576 #global-interrupts = <0>;
1577 #iommu-cells = <1>;
1583 * GPU-GX GDSC's parent is GPU-CX. We need to bring up the
1584 * GPU-CX for SMMU but we need both of them up for Adreno.
1590 power-domains = <&gpucc GPU_GX_GDSC>;
1594 gpucc: clock-controller@5065000 {
1595 compatible = "qcom,msm8998-gpucc";
1596 #clock-cells = <1>;
1597 #reset-cells = <1>;
1598 #power-domain-cells = <1>;
1603 clock-names = "xo",
1608 compatible = "qcom,msm8998-slpi-pas";
1611 interrupts-extended = <&intc GIC_SPI 390 IRQ_TYPE_EDGE_RISING>,
1616 interrupt-names = "wdog", "fatal", "ready",
1617 "handover", "stop-ack";
1619 px-supply = <&vreg_lvs2a_1p8>;
1623 clock-names = "xo", "aggre2";
1625 memory-region = <&slpi_mem>;
1627 qcom,smem-states = <&slpi_smp2p_out 0>;
1628 qcom,smem-state-names = "stop";
1630 power-domains = <&rpmpd MSM8998_SSCCX>;
1631 power-domain-names = "ssc_cx";
1635 glink-edge {
1638 qcom,remote-pid = <3>;
1644 compatible = "arm,coresight-stm", "arm,primecell";
1647 reg-names = "stm-base", "stm-stimulus-base";
1651 clock-names = "apb_pclk", "atclk";
1653 out-ports {
1656 remote-endpoint = <&funnel0_in7>;
1663 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1668 clock-names = "apb_pclk", "atclk";
1670 out-ports {
1673 remote-endpoint =
1679 in-ports {
1680 #address-cells = <1>;
1681 #size-cells = <0>;
1686 remote-endpoint = <&stm_out>;
1693 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1698 clock-names = "apb_pclk", "atclk";
1700 out-ports {
1703 remote-endpoint =
1709 in-ports {
1710 #address-cells = <1>;
1711 #size-cells = <0>;
1716 remote-endpoint =
1724 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
1729 clock-names = "apb_pclk", "atclk";
1731 out-ports {
1734 remote-endpoint =
1740 in-ports {
1741 #address-cells = <1>;
1742 #size-cells = <0>;
1747 remote-endpoint =
1755 remote-endpoint =
1763 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
1768 clock-names = "apb_pclk", "atclk";
1770 out-ports {
1773 remote-endpoint = <&etr_in>;
1778 in-ports {
1781 remote-endpoint = <&etf_out>;
1788 compatible = "arm,coresight-tmc", "arm,primecell";
1793 clock-names = "apb_pclk", "atclk";
1795 out-ports {
1798 remote-endpoint =
1804 in-ports {
1807 remote-endpoint =
1815 compatible = "arm,coresight-tmc", "arm,primecell";
1820 clock-names = "apb_pclk", "atclk";
1821 arm,scatter-gather;
1823 in-ports {
1826 remote-endpoint =
1834 compatible = "arm,coresight-etm4x", "arm,primecell";
1839 clock-names = "apb_pclk", "atclk";
1843 out-ports {
1846 remote-endpoint =
1854 compatible = "arm,coresight-etm4x", "arm,primecell";
1859 clock-names = "apb_pclk", "atclk";
1863 out-ports {
1866 remote-endpoint =
1874 compatible = "arm,coresight-etm4x", "arm,primecell";
1879 clock-names = "apb_pclk", "atclk";
1883 out-ports {
1886 remote-endpoint =
1894 compatible = "arm,coresight-etm4x", "arm,primecell";
1899 clock-names = "apb_pclk", "atclk";
1903 out-ports {
1906 remote-endpoint =
1914 compatible = "arm,coresight-etm4x", "arm,primecell";
1919 clock-names = "apb_pclk", "atclk";
1921 out-ports {
1924 remote-endpoint =
1930 in-ports {
1931 #address-cells = <1>;
1932 #size-cells = <0>;
1937 remote-endpoint =
1945 remote-endpoint =
1953 remote-endpoint =
1961 remote-endpoint =
1969 remote-endpoint =
1977 remote-endpoint =
1985 remote-endpoint =
1993 remote-endpoint =
2001 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2006 clock-names = "apb_pclk", "atclk";
2008 out-ports {
2011 remote-endpoint =
2017 in-ports {
2020 remote-endpoint =
2028 compatible = "arm,coresight-etm4x", "arm,primecell";
2033 clock-names = "apb_pclk", "atclk";
2039 remote-endpoint = <&apss_funnel_in4>;
2045 compatible = "arm,coresight-etm4x", "arm,primecell";
2050 clock-names = "apb_pclk", "atclk";
2056 remote-endpoint = <&apss_funnel_in5>;
2062 compatible = "arm,coresight-etm4x", "arm,primecell";
2067 clock-names = "apb_pclk", "atclk";
2073 remote-endpoint = <&apss_funnel_in6>;
2079 compatible = "arm,coresight-etm4x", "arm,primecell";
2084 clock-names = "apb_pclk", "atclk";
2090 remote-endpoint = <&apss_funnel_in7>;
2096 compatible = "qcom,rpm-stats";
2101 compatible = "qcom,spmi-pmic-arb";
2107 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
2108 interrupt-names = "periph_irq";
2112 #address-cells = <2>;
2113 #size-cells = <0>;
2114 interrupt-controller;
2115 #interrupt-cells = <4>;
2119 compatible = "qcom,msm8998-dwc3", "qcom,dwc3";
2122 #address-cells = <1>;
2123 #size-cells = <1>;
2131 clock-names = "cfg_noc",
2137 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
2139 assigned-clock-rates = <19200000>, <120000000>;
2143 interrupt-names = "hs_phy_irq", "ss_phy_irq";
2145 power-domains = <&gcc USB_30_GDSC>;
2156 phy-names = "usb2-phy", "usb3-phy";
2157 snps,has-lpm-erratum;
2158 snps,hird-threshold = /bits/ 8 <0x10>;
2163 compatible = "qcom,msm8998-qmp-usb3-phy";
2166 #address-cells = <1>;
2167 #size-cells = <1>;
2173 clock-names = "aux", "cfg_ahb", "ref";
2177 reset-names = "phy", "common";
2185 #phy-cells = <0>;
2186 #clock-cells = <0>;
2188 clock-names = "pipe0";
2189 clock-output-names = "usb3_phy_pipe_clk_src";
2194 compatible = "qcom,msm8998-qusb2-phy";
2197 #phy-cells = <0>;
2201 clock-names = "cfg_ahb", "ref";
2205 nvmem-cells = <&qusb2_hstx_trim>;
2209 compatible = "qcom,msm8998-sdhci", "qcom,sdhci-msm-v4";
2211 reg-names = "hc", "core";
2215 interrupt-names = "hc_irq", "pwr_irq";
2217 clock-names = "iface", "core", "xo";
2221 bus-width = <4>;
2225 blsp1_dma: dma-controller@c144000 {
2226 compatible = "qcom,bam-v1.7.0";
2230 clock-names = "bam_clk";
2231 #dma-cells = <1>;
2233 qcom,controlled-remotely;
2234 num-channels = <18>;
2235 qcom,num-ees = <4>;
2239 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2244 clock-names = "core", "iface";
2246 dma-names = "tx", "rx";
2247 pinctrl-names = "default";
2248 pinctrl-0 = <&blsp1_uart3_on>;
2253 compatible = "qcom,i2c-qup-v2.2.1";
2259 clock-names = "core", "iface";
2261 dma-names = "tx", "rx";
2262 pinctrl-names = "default", "sleep";
2263 pinctrl-0 = <&blsp1_i2c1_default>;
2264 pinctrl-1 = <&blsp1_i2c1_sleep>;
2265 clock-frequency = <400000>;
2268 #address-cells = <1>;
2269 #size-cells = <0>;
2273 compatible = "qcom,i2c-qup-v2.2.1";
2279 clock-names = "core", "iface";
2281 dma-names = "tx", "rx";
2282 pinctrl-names = "default", "sleep";
2283 pinctrl-0 = <&blsp1_i2c2_default>;
2284 pinctrl-1 = <&blsp1_i2c2_sleep>;
2285 clock-frequency = <400000>;
2288 #address-cells = <1>;
2289 #size-cells = <0>;
2293 compatible = "qcom,i2c-qup-v2.2.1";
2299 clock-names = "core", "iface";
2301 dma-names = "tx", "rx";
2302 pinctrl-names = "default", "sleep";
2303 pinctrl-0 = <&blsp1_i2c3_default>;
2304 pinctrl-1 = <&blsp1_i2c3_sleep>;
2305 clock-frequency = <400000>;
2308 #address-cells = <1>;
2309 #size-cells = <0>;
2313 compatible = "qcom,i2c-qup-v2.2.1";
2319 clock-names = "core", "iface";
2321 dma-names = "tx", "rx";
2322 pinctrl-names = "default", "sleep";
2323 pinctrl-0 = <&blsp1_i2c4_default>;
2324 pinctrl-1 = <&blsp1_i2c4_sleep>;
2325 clock-frequency = <400000>;
2328 #address-cells = <1>;
2329 #size-cells = <0>;
2333 compatible = "qcom,i2c-qup-v2.2.1";
2339 clock-names = "core", "iface";
2341 dma-names = "tx", "rx";
2342 pinctrl-names = "default", "sleep";
2343 pinctrl-0 = <&blsp1_i2c5_default>;
2344 pinctrl-1 = <&blsp1_i2c5_sleep>;
2345 clock-frequency = <400000>;
2348 #address-cells = <1>;
2349 #size-cells = <0>;
2353 compatible = "qcom,i2c-qup-v2.2.1";
2359 clock-names = "core", "iface";
2361 dma-names = "tx", "rx";
2362 pinctrl-names = "default", "sleep";
2363 pinctrl-0 = <&blsp1_i2c6_default>;
2364 pinctrl-1 = <&blsp1_i2c6_sleep>;
2365 clock-frequency = <400000>;
2368 #address-cells = <1>;
2369 #size-cells = <0>;
2373 compatible = "qcom,spi-qup-v2.2.1";
2379 clock-names = "core", "iface";
2381 dma-names = "tx", "rx";
2382 pinctrl-names = "default";
2383 pinctrl-0 = <&blsp1_spi1_default>;
2386 #address-cells = <1>;
2387 #size-cells = <0>;
2391 compatible = "qcom,spi-qup-v2.2.1";
2397 clock-names = "core", "iface";
2399 dma-names = "tx", "rx";
2400 pinctrl-names = "default";
2401 pinctrl-0 = <&blsp1_spi2_default>;
2404 #address-cells = <1>;
2405 #size-cells = <0>;
2409 compatible = "qcom,spi-qup-v2.2.1";
2415 clock-names = "core", "iface";
2417 dma-names = "tx", "rx";
2418 pinctrl-names = "default";
2419 pinctrl-0 = <&blsp1_spi3_default>;
2422 #address-cells = <1>;
2423 #size-cells = <0>;
2427 compatible = "qcom,spi-qup-v2.2.1";
2433 clock-names = "core", "iface";
2435 dma-names = "tx", "rx";
2436 pinctrl-names = "default";
2437 pinctrl-0 = <&blsp1_spi4_default>;
2440 #address-cells = <1>;
2441 #size-cells = <0>;
2445 compatible = "qcom,spi-qup-v2.2.1";
2451 clock-names = "core", "iface";
2453 dma-names = "tx", "rx";
2454 pinctrl-names = "default";
2455 pinctrl-0 = <&blsp1_spi5_default>;
2458 #address-cells = <1>;
2459 #size-cells = <0>;
2463 compatible = "qcom,spi-qup-v2.2.1";
2469 clock-names = "core", "iface";
2471 dma-names = "tx", "rx";
2472 pinctrl-names = "default";
2473 pinctrl-0 = <&blsp1_spi6_default>;
2476 #address-cells = <1>;
2477 #size-cells = <0>;
2480 blsp2_dma: dma-controller@c184000 {
2481 compatible = "qcom,bam-v1.7.0";
2485 clock-names = "bam_clk";
2486 #dma-cells = <1>;
2488 qcom,controlled-remotely;
2489 num-channels = <18>;
2490 qcom,num-ees = <4>;
2494 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
2499 clock-names = "core", "iface";
2504 compatible = "qcom,i2c-qup-v2.2.1";
2510 clock-names = "core", "iface";
2512 dma-names = "tx", "rx";
2513 pinctrl-names = "default", "sleep";
2514 pinctrl-0 = <&blsp2_i2c1_default>;
2515 pinctrl-1 = <&blsp2_i2c1_sleep>;
2516 clock-frequency = <400000>;
2519 #address-cells = <1>;
2520 #size-cells = <0>;
2524 compatible = "qcom,i2c-qup-v2.2.1";
2530 clock-names = "core", "iface";
2532 dma-names = "tx", "rx";
2533 pinctrl-names = "default", "sleep";
2534 pinctrl-0 = <&blsp2_i2c2_default>;
2535 pinctrl-1 = <&blsp2_i2c2_sleep>;
2536 clock-frequency = <400000>;
2539 #address-cells = <1>;
2540 #size-cells = <0>;
2544 compatible = "qcom,i2c-qup-v2.2.1";
2550 clock-names = "core", "iface";
2552 dma-names = "tx", "rx";
2553 pinctrl-names = "default", "sleep";
2554 pinctrl-0 = <&blsp2_i2c3_default>;
2555 pinctrl-1 = <&blsp2_i2c3_sleep>;
2556 clock-frequency = <400000>;
2559 #address-cells = <1>;
2560 #size-cells = <0>;
2564 compatible = "qcom,i2c-qup-v2.2.1";
2570 clock-names = "core", "iface";
2572 dma-names = "tx", "rx";
2573 pinctrl-names = "default", "sleep";
2574 pinctrl-0 = <&blsp2_i2c4_default>;
2575 pinctrl-1 = <&blsp2_i2c4_sleep>;
2576 clock-frequency = <400000>;
2579 #address-cells = <1>;
2580 #size-cells = <0>;
2584 compatible = "qcom,i2c-qup-v2.2.1";
2590 clock-names = "core", "iface";
2592 dma-names = "tx", "rx";
2593 pinctrl-names = "default", "sleep";
2594 pinctrl-0 = <&blsp2_i2c5_default>;
2595 pinctrl-1 = <&blsp2_i2c5_sleep>;
2596 clock-frequency = <400000>;
2599 #address-cells = <1>;
2600 #size-cells = <0>;
2604 compatible = "qcom,i2c-qup-v2.2.1";
2610 clock-names = "core", "iface";
2612 dma-names = "tx", "rx";
2613 pinctrl-names = "default", "sleep";
2614 pinctrl-0 = <&blsp2_i2c6_default>;
2615 pinctrl-1 = <&blsp2_i2c6_sleep>;
2616 clock-frequency = <400000>;
2619 #address-cells = <1>;
2620 #size-cells = <0>;
2624 compatible = "qcom,spi-qup-v2.2.1";
2630 clock-names = "core", "iface";
2632 dma-names = "tx", "rx";
2633 pinctrl-names = "default";
2634 pinctrl-0 = <&blsp2_spi1_default>;
2637 #address-cells = <1>;
2638 #size-cells = <0>;
2642 compatible = "qcom,spi-qup-v2.2.1";
2648 clock-names = "core", "iface";
2650 dma-names = "tx", "rx";
2651 pinctrl-names = "default";
2652 pinctrl-0 = <&blsp2_spi2_default>;
2655 #address-cells = <1>;
2656 #size-cells = <0>;
2660 compatible = "qcom,spi-qup-v2.2.1";
2666 clock-names = "core", "iface";
2668 dma-names = "tx", "rx";
2669 pinctrl-names = "default";
2670 pinctrl-0 = <&blsp2_spi3_default>;
2673 #address-cells = <1>;
2674 #size-cells = <0>;
2678 compatible = "qcom,spi-qup-v2.2.1";
2684 clock-names = "core", "iface";
2686 dma-names = "tx", "rx";
2687 pinctrl-names = "default";
2688 pinctrl-0 = <&blsp2_spi4_default>;
2691 #address-cells = <1>;
2692 #size-cells = <0>;
2696 compatible = "qcom,spi-qup-v2.2.1";
2702 clock-names = "core", "iface";
2704 dma-names = "tx", "rx";
2705 pinctrl-names = "default";
2706 pinctrl-0 = <&blsp2_spi5_default>;
2709 #address-cells = <1>;
2710 #size-cells = <0>;
2714 compatible = "qcom,spi-qup-v2.2.1";
2720 clock-names = "core", "iface";
2722 dma-names = "tx", "rx";
2723 pinctrl-names = "default";
2724 pinctrl-0 = <&blsp2_spi6_default>;
2727 #address-cells = <1>;
2728 #size-cells = <0>;
2731 mmcc: clock-controller@c8c0000 {
2732 compatible = "qcom,mmcc-msm8998";
2733 #clock-cells = <1>;
2734 #reset-cells = <1>;
2735 #power-domain-cells = <1>;
2738 clock-names = "xo",
2760 mdss: display-subsystem@c900000 {
2761 compatible = "qcom,msm8998-mdss";
2763 reg-names = "mdss";
2766 interrupt-controller;
2767 #interrupt-cells = <1>;
2772 clock-names = "iface",
2776 power-domains = <&mmcc MDSS_GDSC>;
2779 #address-cells = <1>;
2780 #size-cells = <1>;
2785 mdss_mdp: display-controller@c901000 {
2786 compatible = "qcom,msm8998-dpu";
2791 reg-names = "mdp",
2796 interrupt-parent = <&mdss>;
2804 clock-names = "iface",
2810 assigned-clocks = <&mmcc MDSS_VSYNC_CLK>;
2811 assigned-clock-rates = <19200000>;
2813 operating-points-v2 = <&mdp_opp_table>;
2814 power-domains = <&rpmpd MSM8998_VDDMX>;
2816 mdp_opp_table: opp-table {
2817 compatible = "operating-points-v2";
2819 opp-171430000 {
2820 opp-hz = /bits/ 64 <171430000>;
2821 required-opps = <&rpmpd_opp_low_svs>;
2824 opp-275000000 {
2825 opp-hz = /bits/ 64 <275000000>;
2826 required-opps = <&rpmpd_opp_svs>;
2829 opp-330000000 {
2830 opp-hz = /bits/ 64 <330000000>;
2831 required-opps = <&rpmpd_opp_nom>;
2834 opp-412500000 {
2835 opp-hz = /bits/ 64 <412500000>;
2836 required-opps = <&rpmpd_opp_turbo>;
2841 #address-cells = <1>;
2842 #size-cells = <0>;
2848 remote-endpoint = <&mdss_dsi0_in>;
2856 remote-endpoint = <&mdss_dsi1_in>;
2863 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2865 reg-names = "dsi_ctrl";
2867 interrupt-parent = <&mdss>;
2876 clock-names = "byte",
2882 assigned-clocks = <&mmcc BYTE0_CLK_SRC>,
2884 assigned-clock-parents = <&mdss_dsi0_phy 0>,
2887 operating-points-v2 = <&dsi_opp_table>;
2888 power-domains = <&rpmpd MSM8998_VDDCX>;
2891 phy-names = "dsi";
2893 #address-cells = <1>;
2894 #size-cells = <0>;
2899 #address-cells = <1>;
2900 #size-cells = <0>;
2906 remote-endpoint = <&dpu_intf1_out>;
2920 compatible = "qcom,dsi-phy-10nm-8998";
2924 reg-names = "dsi_phy",
2930 clock-names = "iface", "ref";
2932 #clock-cells = <1>;
2933 #phy-cells = <0>;
2939 compatible = "qcom,msm8998-dsi-ctrl", "qcom,mdss-dsi-ctrl";
2941 reg-names = "dsi_ctrl";
2943 interrupt-parent = <&mdss>;
2952 clock-names = "byte",
2958 assigned-clocks = <&mmcc BYTE1_CLK_SRC>,
2960 assigned-clock-parents = <&mdss_dsi1_phy 0>,
2963 operating-points-v2 = <&dsi_opp_table>;
2964 power-domains = <&rpmpd MSM8998_VDDCX>;
2967 phy-names = "dsi";
2969 #address-cells = <1>;
2970 #size-cells = <0>;
2975 #address-cells = <1>;
2976 #size-cells = <0>;
2982 remote-endpoint = <&dpu_intf2_out>;
2996 compatible = "qcom,dsi-phy-10nm-8998";
3000 reg-names = "dsi_phy",
3006 clock-names = "iface",
3009 #clock-cells = <1>;
3010 #phy-cells = <0>;
3017 compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
3019 #iommu-cells = <1>;
3024 clock-names = "iface-mm",
3025 "iface-smmu",
3026 "bus-smmu";
3028 #global-interrupts = <0>;
3051 power-domains = <&mmcc BIMC_SMMU_GDSC>;
3055 compatible = "qcom,msm8998-adsp-pas";
3058 interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
3063 interrupt-names = "wdog", "fatal", "ready",
3064 "handover", "stop-ack";
3067 clock-names = "xo";
3069 memory-region = <&adsp_mem>;
3071 qcom,smem-states = <&adsp_smp2p_out 0>;
3072 qcom,smem-state-names = "stop";
3074 power-domains = <&rpmpd MSM8998_VDDCX>;
3075 power-domain-names = "cx";
3079 glink-edge {
3082 qcom,remote-pid = <2>;
3088 compatible = "qcom,msm8998-apcs-hmss-global",
3089 "qcom,msm8994-apcs-kpss-global";
3092 #mbox-cells = <1>;
3096 #address-cells = <1>;
3097 #size-cells = <1>;
3099 compatible = "arm,armv7-timer-mem";
3103 frame-number = <0>;
3111 frame-number = <1>;
3118 frame-number = <2>;
3125 frame-number = <3>;
3132 frame-number = <4>;
3139 frame-number = <5>;
3146 frame-number = <6>;
3153 intc: interrupt-controller@17a00000 {
3154 compatible = "arm,gic-v3";
3157 #interrupt-cells = <3>;
3158 #address-cells = <1>;
3159 #size-cells = <1>;
3161 interrupt-controller;
3162 #redistributor-regions = <1>;
3163 redistributor-stride = <0x0 0x20000>;
3168 compatible = "qcom,wcn3990-wifi";
3171 reg-names = "membase";
3172 memory-region = <&wlan_msa_mem>;
3174 clock-names = "cxo_ref_clk_pin";
3190 qcom,snoc-host-cap-8bit-quirk;