Lines Matching refs:mmcc
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
908 <&mmcc AHB_CLK_SRC>;
936 mmcc: clock-controller@8c0000 { label
937 compatible = "qcom,mmcc-msm8996";
958 assigned-clocks = <&mmcc MMPLL9_PLL>,
959 <&mmcc MMPLL1_PLL>,
960 <&mmcc MMPLL3_PLL>,
961 <&mmcc MMPLL4_PLL>,
962 <&mmcc MMPLL5_PLL>;
980 power-domains = <&mmcc MDSS_GDSC>;
986 clocks = <&mmcc MDSS_AHB_CLK>,
987 <&mmcc MDSS_MDP_CLK>;
1004 clocks = <&mmcc MDSS_AHB_CLK>,
1005 <&mmcc MDSS_AXI_CLK>,
1006 <&mmcc MDSS_MDP_CLK>,
1007 <&mmcc SMMU_MDP_AXI_CLK>,
1008 <&mmcc MDSS_VSYNC_CLK>;
1017 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1018 <&mmcc MDSS_VSYNC_CLK>;
1063 clocks = <&mmcc MDSS_MDP_CLK>,
1064 <&mmcc MDSS_BYTE0_CLK>,
1065 <&mmcc MDSS_AHB_CLK>,
1066 <&mmcc MDSS_AXI_CLK>,
1067 <&mmcc MMSS_MISC_AHB_CLK>,
1068 <&mmcc MDSS_PCLK0_CLK>,
1069 <&mmcc MDSS_ESC0_CLK>;
1077 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1117 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1131 clocks = <&mmcc MDSS_MDP_CLK>,
1132 <&mmcc MDSS_BYTE1_CLK>,
1133 <&mmcc MDSS_AHB_CLK>,
1134 <&mmcc MDSS_AXI_CLK>,
1135 <&mmcc MMSS_MISC_AHB_CLK>,
1136 <&mmcc MDSS_PCLK1_CLK>,
1137 <&mmcc MDSS_ESC1_CLK>;
1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1185 clocks = <&mmcc MDSS_AHB_CLK>, <&rpmcc RPM_SMD_XO_CLK_SRC>;
1202 clocks = <&mmcc MDSS_MDP_CLK>,
1203 <&mmcc MDSS_AHB_CLK>,
1204 <&mmcc MDSS_HDMI_CLK>,
1205 <&mmcc MDSS_HDMI_AHB_CLK>,
1206 <&mmcc MDSS_EXTPCLK_CLK>;
1248 clocks = <&mmcc MDSS_AHB_CLK>,
1269 clocks = <&mmcc GPU_GX_GFX3D_CLK>,
1270 <&mmcc GPU_AHB_CLK>,
1271 <&mmcc GPU_GX_RBBMTIMER_CLK>,
1284 power-domains = <&mmcc GPU_GX_GDSC>;
2173 power-domains = <&mmcc VFE0_GDSC>,
2174 <&mmcc VFE1_GDSC>;
2175 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2176 <&mmcc CAMSS_ISPIF_AHB_CLK>,
2177 <&mmcc CAMSS_CSI0PHYTIMER_CLK>,
2178 <&mmcc CAMSS_CSI1PHYTIMER_CLK>,
2179 <&mmcc CAMSS_CSI2PHYTIMER_CLK>,
2180 <&mmcc CAMSS_CSI0_AHB_CLK>,
2181 <&mmcc CAMSS_CSI0_CLK>,
2182 <&mmcc CAMSS_CSI0PHY_CLK>,
2183 <&mmcc CAMSS_CSI0PIX_CLK>,
2184 <&mmcc CAMSS_CSI0RDI_CLK>,
2185 <&mmcc CAMSS_CSI1_AHB_CLK>,
2186 <&mmcc CAMSS_CSI1_CLK>,
2187 <&mmcc CAMSS_CSI1PHY_CLK>,
2188 <&mmcc CAMSS_CSI1PIX_CLK>,
2189 <&mmcc CAMSS_CSI1RDI_CLK>,
2190 <&mmcc CAMSS_CSI2_AHB_CLK>,
2191 <&mmcc CAMSS_CSI2_CLK>,
2192 <&mmcc CAMSS_CSI2PHY_CLK>,
2193 <&mmcc CAMSS_CSI2PIX_CLK>,
2194 <&mmcc CAMSS_CSI2RDI_CLK>,
2195 <&mmcc CAMSS_CSI3_AHB_CLK>,
2196 <&mmcc CAMSS_CSI3_CLK>,
2197 <&mmcc CAMSS_CSI3PHY_CLK>,
2198 <&mmcc CAMSS_CSI3PIX_CLK>,
2199 <&mmcc CAMSS_CSI3RDI_CLK>,
2200 <&mmcc CAMSS_AHB_CLK>,
2201 <&mmcc CAMSS_VFE0_CLK>,
2202 <&mmcc CAMSS_CSI_VFE0_CLK>,
2203 <&mmcc CAMSS_VFE0_AHB_CLK>,
2204 <&mmcc CAMSS_VFE0_STREAM_CLK>,
2205 <&mmcc CAMSS_VFE1_CLK>,
2206 <&mmcc CAMSS_CSI_VFE1_CLK>,
2207 <&mmcc CAMSS_VFE1_AHB_CLK>,
2208 <&mmcc CAMSS_VFE1_STREAM_CLK>,
2209 <&mmcc CAMSS_VFE_AHB_CLK>,
2210 <&mmcc CAMSS_VFE_AXI_CLK>;
2264 power-domains = <&mmcc CAMSS_GDSC>;
2265 clocks = <&mmcc CAMSS_TOP_AHB_CLK>,
2266 <&mmcc CAMSS_CCI_AHB_CLK>,
2267 <&mmcc CAMSS_CCI_CLK>,
2268 <&mmcc CAMSS_AHB_CLK>;
2273 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2274 <&mmcc CAMSS_CCI_CLK>;
2306 <&mmcc GPU_AHB_CLK>;
2309 power-domains = <&mmcc GPU_GDSC>;
2316 power-domains = <&mmcc VENUS_GDSC>;
2317 clocks = <&mmcc VIDEO_CORE_CLK>,
2318 <&mmcc VIDEO_AHB_CLK>,
2319 <&mmcc VIDEO_AXI_CLK>,
2320 <&mmcc VIDEO_MAXI_CLK>;
2350 clocks = <&mmcc VIDEO_SUBCORE0_CLK>;
2352 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2357 clocks = <&mmcc VIDEO_SUBCORE1_CLK>;
2359 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2372 clocks = <&mmcc SMMU_MDP_AXI_CLK>,
2373 <&mmcc SMMU_MDP_AHB_CLK>;
2376 power-domains = <&mmcc MDSS_GDSC>;
2391 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2392 clocks = <&mmcc SMMU_VIDEO_AXI_CLK>,
2393 <&mmcc SMMU_VIDEO_AHB_CLK>;
2407 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2408 clocks = <&mmcc SMMU_VFE_AXI_CLK>,
2409 <&mmcc SMMU_VFE_AHB_CLK>;