Lines Matching +full:opp +full:- +full:v2 +full:- +full:base
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/qcom,gcc-msm8996.h>
8 #include <dt-bindings/clock/qcom,mmcc-msm8996.h>
9 #include <dt-bindings/clock/qcom,rpmcc.h>
10 #include <dt-bindings/interconnect/qcom,msm8996.h>
11 #include <dt-bindings/interconnect/qcom,msm8996-cbf.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,apr.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&intc>;
20 #address-cells = <2>;
21 #size-cells = <2>;
26 xo_board: xo-board {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
29 clock-frequency = <19200000>;
30 clock-output-names = "xo_board";
33 sleep_clk: sleep-clk {
34 compatible = "fixed-clock";
35 #clock-cells = <0>;
36 clock-frequency = <32764>;
37 clock-output-names = "sleep_clk";
42 #address-cells = <2>;
43 #size-cells = <0>;
49 enable-method = "psci";
50 cpu-idle-states = <&CPU_SLEEP_0>;
51 capacity-dmips-mhz = <1024>;
54 operating-points-v2 = <&cluster0_opp>;
55 #cooling-cells = <2>;
56 next-level-cache = <&L2_0>;
57 L2_0: l2-cache {
59 cache-level = <2>;
60 cache-unified;
68 enable-method = "psci";
69 cpu-idle-states = <&CPU_SLEEP_0>;
70 capacity-dmips-mhz = <1024>;
73 operating-points-v2 = <&cluster0_opp>;
74 #cooling-cells = <2>;
75 next-level-cache = <&L2_0>;
82 enable-method = "psci";
83 cpu-idle-states = <&CPU_SLEEP_0>;
84 capacity-dmips-mhz = <1024>;
87 operating-points-v2 = <&cluster1_opp>;
88 #cooling-cells = <2>;
89 next-level-cache = <&L2_1>;
90 L2_1: l2-cache {
92 cache-level = <2>;
93 cache-unified;
101 enable-method = "psci";
102 cpu-idle-states = <&CPU_SLEEP_0>;
103 capacity-dmips-mhz = <1024>;
106 operating-points-v2 = <&cluster1_opp>;
107 #cooling-cells = <2>;
108 next-level-cache = <&L2_1>;
111 cpu-map {
133 idle-states {
134 entry-method = "psci";
136 CPU_SLEEP_0: cpu-sleep-0 {
137 compatible = "arm,idle-state";
138 idle-state-name = "standalone-power-collapse";
139 arm,psci-suspend-param = <0x00000004>;
140 entry-latency-us = <130>;
141 exit-latency-us = <80>;
142 min-residency-us = <300>;
147 cluster0_opp: opp-table-cluster0 {
148 compatible = "operating-points-v2-kryo-cpu";
149 nvmem-cells = <&speedbin_efuse>;
150 opp-shared;
153 opp-307200000 {
154 opp-hz = /bits/ 64 <307200000>;
155 opp-supported-hw = <0xf>;
156 clock-latency-ns = <200000>;
157 opp-peak-kBps = <307200>;
159 opp-422400000 {
160 opp-hz = /bits/ 64 <422400000>;
161 opp-supported-hw = <0xf>;
162 clock-latency-ns = <200000>;
163 opp-peak-kBps = <307200>;
165 opp-480000000 {
166 opp-hz = /bits/ 64 <480000000>;
167 opp-supported-hw = <0xf>;
168 clock-latency-ns = <200000>;
169 opp-peak-kBps = <307200>;
171 opp-556800000 {
172 opp-hz = /bits/ 64 <556800000>;
173 opp-supported-hw = <0xf>;
174 clock-latency-ns = <200000>;
175 opp-peak-kBps = <307200>;
177 opp-652800000 {
178 opp-hz = /bits/ 64 <652800000>;
179 opp-supported-hw = <0xf>;
180 clock-latency-ns = <200000>;
181 opp-peak-kBps = <384000>;
183 opp-729600000 {
184 opp-hz = /bits/ 64 <729600000>;
185 opp-supported-hw = <0xf>;
186 clock-latency-ns = <200000>;
187 opp-peak-kBps = <460800>;
189 opp-844800000 {
190 opp-hz = /bits/ 64 <844800000>;
191 opp-supported-hw = <0xf>;
192 clock-latency-ns = <200000>;
193 opp-peak-kBps = <537600>;
195 opp-960000000 {
196 opp-hz = /bits/ 64 <960000000>;
197 opp-supported-hw = <0xf>;
198 clock-latency-ns = <200000>;
199 opp-peak-kBps = <672000>;
201 opp-1036800000 {
202 opp-hz = /bits/ 64 <1036800000>;
203 opp-supported-hw = <0xf>;
204 clock-latency-ns = <200000>;
205 opp-peak-kBps = <672000>;
207 opp-1113600000 {
208 opp-hz = /bits/ 64 <1113600000>;
209 opp-supported-hw = <0xf>;
210 clock-latency-ns = <200000>;
211 opp-peak-kBps = <825600>;
213 opp-1190400000 {
214 opp-hz = /bits/ 64 <1190400000>;
215 opp-supported-hw = <0xf>;
216 clock-latency-ns = <200000>;
217 opp-peak-kBps = <825600>;
219 opp-1228800000 {
220 opp-hz = /bits/ 64 <1228800000>;
221 opp-supported-hw = <0xf>;
222 clock-latency-ns = <200000>;
223 opp-peak-kBps = <902400>;
225 opp-1324800000 {
226 opp-hz = /bits/ 64 <1324800000>;
227 opp-supported-hw = <0xd>;
228 clock-latency-ns = <200000>;
229 opp-peak-kBps = <1056000>;
231 opp-1363200000 {
232 opp-hz = /bits/ 64 <1363200000>;
233 opp-supported-hw = <0x2>;
234 clock-latency-ns = <200000>;
235 opp-peak-kBps = <1132800>;
237 opp-1401600000 {
238 opp-hz = /bits/ 64 <1401600000>;
239 opp-supported-hw = <0xd>;
240 clock-latency-ns = <200000>;
241 opp-peak-kBps = <1132800>;
243 opp-1478400000 {
244 opp-hz = /bits/ 64 <1478400000>;
245 opp-supported-hw = <0x9>;
246 clock-latency-ns = <200000>;
247 opp-peak-kBps = <1190400>;
249 opp-1497600000 {
250 opp-hz = /bits/ 64 <1497600000>;
251 opp-supported-hw = <0x04>;
252 clock-latency-ns = <200000>;
253 opp-peak-kBps = <1305600>;
255 opp-1593600000 {
256 opp-hz = /bits/ 64 <1593600000>;
257 opp-supported-hw = <0x9>;
258 clock-latency-ns = <200000>;
259 opp-peak-kBps = <1382400>;
263 cluster1_opp: opp-table-cluster1 {
264 compatible = "operating-points-v2-kryo-cpu";
265 nvmem-cells = <&speedbin_efuse>;
266 opp-shared;
269 opp-307200000 {
270 opp-hz = /bits/ 64 <307200000>;
271 opp-supported-hw = <0xf>;
272 clock-latency-ns = <200000>;
273 opp-peak-kBps = <307200>;
275 opp-403200000 {
276 opp-hz = /bits/ 64 <403200000>;
277 opp-supported-hw = <0xf>;
278 clock-latency-ns = <200000>;
279 opp-peak-kBps = <307200>;
281 opp-480000000 {
282 opp-hz = /bits/ 64 <480000000>;
283 opp-supported-hw = <0xf>;
284 clock-latency-ns = <200000>;
285 opp-peak-kBps = <307200>;
287 opp-556800000 {
288 opp-hz = /bits/ 64 <556800000>;
289 opp-supported-hw = <0xf>;
290 clock-latency-ns = <200000>;
291 opp-peak-kBps = <307200>;
293 opp-652800000 {
294 opp-hz = /bits/ 64 <652800000>;
295 opp-supported-hw = <0xf>;
296 clock-latency-ns = <200000>;
297 opp-peak-kBps = <307200>;
299 opp-729600000 {
300 opp-hz = /bits/ 64 <729600000>;
301 opp-supported-hw = <0xf>;
302 clock-latency-ns = <200000>;
303 opp-peak-kBps = <307200>;
305 opp-806400000 {
306 opp-hz = /bits/ 64 <806400000>;
307 opp-supported-hw = <0xf>;
308 clock-latency-ns = <200000>;
309 opp-peak-kBps = <384000>;
311 opp-883200000 {
312 opp-hz = /bits/ 64 <883200000>;
313 opp-supported-hw = <0xf>;
314 clock-latency-ns = <200000>;
315 opp-peak-kBps = <460800>;
317 opp-940800000 {
318 opp-hz = /bits/ 64 <940800000>;
319 opp-supported-hw = <0xf>;
320 clock-latency-ns = <200000>;
321 opp-peak-kBps = <537600>;
323 opp-1036800000 {
324 opp-hz = /bits/ 64 <1036800000>;
325 opp-supported-hw = <0xf>;
326 clock-latency-ns = <200000>;
327 opp-peak-kBps = <595200>;
329 opp-1113600000 {
330 opp-hz = /bits/ 64 <1113600000>;
331 opp-supported-hw = <0xf>;
332 clock-latency-ns = <200000>;
333 opp-peak-kBps = <672000>;
335 opp-1190400000 {
336 opp-hz = /bits/ 64 <1190400000>;
337 opp-supported-hw = <0xf>;
338 clock-latency-ns = <200000>;
339 opp-peak-kBps = <672000>;
341 opp-1248000000 {
342 opp-hz = /bits/ 64 <1248000000>;
343 opp-supported-hw = <0xf>;
344 clock-latency-ns = <200000>;
345 opp-peak-kBps = <748800>;
347 opp-1324800000 {
348 opp-hz = /bits/ 64 <1324800000>;
349 opp-supported-hw = <0xf>;
350 clock-latency-ns = <200000>;
351 opp-peak-kBps = <825600>;
353 opp-1401600000 {
354 opp-hz = /bits/ 64 <1401600000>;
355 opp-supported-hw = <0xf>;
356 clock-latency-ns = <200000>;
357 opp-peak-kBps = <902400>;
359 opp-1478400000 {
360 opp-hz = /bits/ 64 <1478400000>;
361 opp-supported-hw = <0xf>;
362 clock-latency-ns = <200000>;
363 opp-peak-kBps = <979200>;
365 opp-1555200000 {
366 opp-hz = /bits/ 64 <1555200000>;
367 opp-supported-hw = <0xf>;
368 clock-latency-ns = <200000>;
369 opp-peak-kBps = <1056000>;
371 opp-1632000000 {
372 opp-hz = /bits/ 64 <1632000000>;
373 opp-supported-hw = <0xf>;
374 clock-latency-ns = <200000>;
375 opp-peak-kBps = <1190400>;
377 opp-1708800000 {
378 opp-hz = /bits/ 64 <1708800000>;
379 opp-supported-hw = <0xf>;
380 clock-latency-ns = <200000>;
381 opp-peak-kBps = <1228800>;
383 opp-1785600000 {
384 opp-hz = /bits/ 64 <1785600000>;
385 opp-supported-hw = <0xf>;
386 clock-latency-ns = <200000>;
387 opp-peak-kBps = <1305600>;
389 opp-1804800000 {
390 opp-hz = /bits/ 64 <1804800000>;
391 opp-supported-hw = <0xe>;
392 clock-latency-ns = <200000>;
393 opp-peak-kBps = <1305600>;
395 opp-1824000000 {
396 opp-hz = /bits/ 64 <1824000000>;
397 opp-supported-hw = <0x1>;
398 clock-latency-ns = <200000>;
399 opp-peak-kBps = <1382400>;
401 opp-1900800000 {
402 opp-hz = /bits/ 64 <1900800000>;
403 opp-supported-hw = <0x4>;
404 clock-latency-ns = <200000>;
405 opp-peak-kBps = <1305600>;
407 opp-1920000000 {
408 opp-hz = /bits/ 64 <1920000000>;
409 opp-supported-hw = <0x1>;
410 clock-latency-ns = <200000>;
411 opp-peak-kBps = <1459200>;
413 opp-1996800000 {
414 opp-hz = /bits/ 64 <1996800000>;
415 opp-supported-hw = <0x1>;
416 clock-latency-ns = <200000>;
417 opp-peak-kBps = <1593600>;
419 opp-2073600000 {
420 opp-hz = /bits/ 64 <2073600000>;
421 opp-supported-hw = <0x1>;
422 clock-latency-ns = <200000>;
423 opp-peak-kBps = <1593600>;
425 opp-2150400000 {
426 opp-hz = /bits/ 64 <2150400000>;
427 opp-supported-hw = <0x1>;
428 clock-latency-ns = <200000>;
429 opp-peak-kBps = <1593600>;
435 compatible = "qcom,scm-msm8996", "qcom,scm";
436 qcom,dload-mode = <&tcsr_2 0x13000>;
447 compatible = "arm,psci-1.0";
452 compatible = "qcom,msm8996-rpm-proc", "qcom,rpm-proc";
454 glink-edge {
455 compatible = "qcom,glink-rpm";
457 qcom,rpm-msg-ram = <&rpm_msg_ram>;
460 rpm_requests: rpm-requests {
461 compatible = "qcom,rpm-msm8996";
462 qcom,glink-channels = "rpm_requests";
464 rpmcc: clock-controller {
465 compatible = "qcom,rpmcc-msm8996", "qcom,rpmcc";
466 #clock-cells = <1>;
468 clock-names = "xo";
471 rpmpd: power-controller {
472 compatible = "qcom,msm8996-rpmpd";
473 #power-domain-cells = <1>;
474 operating-points-v2 = <&rpmpd_opp_table>;
476 rpmpd_opp_table: opp-table {
477 compatible = "operating-points-v2";
480 opp-level = <1>;
484 opp-level = <2>;
488 opp-level = <3>;
492 opp-level = <4>;
496 opp-level = <5>;
500 opp-level = <6>;
508 reserved-memory {
509 #address-cells = <2>;
510 #size-cells = <2>;
515 no-map;
520 no-map;
523 smem_mem: smem-mem@86000000 {
525 no-map;
530 no-map;
534 compatible = "qcom,rmtfs-mem";
537 alloc-ranges = <0x0 0xa0000000 0x0 0x2000000>;
538 no-map;
540 qcom,client-id = <1>;
546 no-map;
551 no-map;
556 no-map;
560 compatible = "shared-dma-pool";
562 no-map;
567 no-map;
572 no-map;
575 mdata_mem: mpss-metadata {
576 alloc-ranges = <0x0 0xa0000000 0x0 0x20000000>;
578 no-map;
584 memory-region = <&smem_mem>;
588 smp2p-adsp {
596 qcom,local-pid = <0>;
597 qcom,remote-pid = <2>;
599 adsp_smp2p_out: master-kernel {
600 qcom,entry-name = "master-kernel";
601 #qcom,smem-state-cells = <1>;
604 adsp_smp2p_in: slave-kernel {
605 qcom,entry-name = "slave-kernel";
607 interrupt-controller;
608 #interrupt-cells = <2>;
612 smp2p-mpss {
620 qcom,local-pid = <0>;
621 qcom,remote-pid = <1>;
623 mpss_smp2p_out: master-kernel {
624 qcom,entry-name = "master-kernel";
625 #qcom,smem-state-cells = <1>;
628 mpss_smp2p_in: slave-kernel {
629 qcom,entry-name = "slave-kernel";
631 interrupt-controller;
632 #interrupt-cells = <2>;
636 smp2p-slpi {
644 qcom,local-pid = <0>;
645 qcom,remote-pid = <3>;
647 slpi_smp2p_out: master-kernel {
648 qcom,entry-name = "master-kernel";
649 #qcom,smem-state-cells = <1>;
652 slpi_smp2p_in: slave-kernel {
653 qcom,entry-name = "slave-kernel";
655 interrupt-controller;
656 #interrupt-cells = <2>;
661 #address-cells = <1>;
662 #size-cells = <1>;
664 compatible = "simple-bus";
666 pcie_phy: phy-wrapper@34000 {
667 compatible = "qcom,msm8996-qmp-pcie-phy";
669 #address-cells = <1>;
670 #size-cells = <1>;
676 clock-names = "aux", "cfg_ahb", "ref";
681 reset-names = "phy", "common", "cfg";
691 clock-names = "pipe0";
693 reset-names = "lane0";
695 #clock-cells = <0>;
696 clock-output-names = "pcie_0_pipe_clk_src";
698 #phy-cells = <0>;
707 clock-names = "pipe1";
709 reset-names = "lane1";
711 #clock-cells = <0>;
712 clock-output-names = "pcie_1_pipe_clk_src";
714 #phy-cells = <0>;
723 clock-names = "pipe2";
725 reset-names = "lane2";
727 #clock-cells = <0>;
728 clock-output-names = "pcie_2_pipe_clk_src";
730 #phy-cells = <0>;
735 compatible = "qcom,rpm-msg-ram";
740 compatible = "qcom,msm8996-qfprom", "qcom,qfprom";
742 #address-cells = <1>;
743 #size-cells = <1>;
762 compatible = "qcom,prng-ee";
765 clock-names = "core";
768 gcc: clock-controller@300000 {
769 compatible = "qcom,gcc-msm8996";
770 #clock-cells = <1>;
771 #reset-cells = <1>;
772 #power-domain-cells = <1>;
785 clock-names = "cxo",
798 compatible = "qcom,msm8996-bimc";
800 #interconnect-cells = <1>;
801 clock-names = "bus", "bus_a";
806 tsens0: thermal-sensor@4a9000 {
807 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
813 interrupt-names = "uplow", "critical";
814 #thermal-sensor-cells = <1>;
817 tsens1: thermal-sensor@4ad000 {
818 compatible = "qcom,msm8996-tsens", "qcom,tsens-v2";
824 interrupt-names = "uplow", "critical";
825 #thermal-sensor-cells = <1>;
828 cryptobam: dma-controller@644000 {
829 compatible = "qcom,bam-v1.7.0";
833 clock-names = "bam_clk";
834 #dma-cells = <1>;
836 qcom,controlled-remotely;
840 compatible = "qcom,crypto-v5.4";
845 clock-names = "iface", "bus", "core";
847 dma-names = "rx", "tx";
851 compatible = "qcom,msm8996-cnoc";
853 #interconnect-cells = <1>;
854 clock-names = "bus", "bus_a";
860 compatible = "qcom,msm8996-snoc";
862 #interconnect-cells = <1>;
863 clock-names = "bus", "bus_a";
869 compatible = "qcom,msm8996-a0noc";
871 #interconnect-cells = <1>;
872 clock-names = "aggre0_snoc_axi",
878 power-domains = <&gcc AGGRE0_NOC_GDSC>;
882 compatible = "qcom,msm8996-a1noc";
884 #interconnect-cells = <1>;
885 clock-names = "bus", "bus_a";
891 compatible = "qcom,msm8996-a2noc";
893 #interconnect-cells = <1>;
894 clock-names = "bus", "bus_a", "aggre2_ufs_axi", "ufs_axi";
902 compatible = "qcom,msm8996-mnoc";
904 #interconnect-cells = <1>;
905 clock-names = "bus", "bus_a", "iface";
912 compatible = "qcom,msm8996-pnoc";
914 #interconnect-cells = <1>;
915 clock-names = "bus", "bus_a";
921 compatible = "qcom,tcsr-mutex";
923 #hwlock-cells = <1>;
927 compatible = "qcom,tcsr-msm8996", "syscon";
932 compatible = "qcom,tcsr-msm8996", "syscon";
936 mmcc: clock-controller@8c0000 {
937 compatible = "qcom,mmcc-msm8996";
938 #clock-cells = <1>;
939 #reset-cells = <1>;
940 #power-domain-cells = <1>;
950 clock-names = "xo",
958 assigned-clocks = <&mmcc MMPLL9_PLL>,
963 assigned-clock-rates = <624000000>,
970 mdss: display-subsystem@900000 {
976 reg-names = "mdss_phys",
980 power-domains = <&mmcc MDSS_GDSC>;
983 interrupt-controller;
984 #interrupt-cells = <1>;
988 clock-names = "iface", "core";
990 #address-cells = <1>;
991 #size-cells = <1>;
996 mdp: display-controller@901000 {
997 compatible = "qcom,msm8996-mdp5", "qcom,mdp5";
999 reg-names = "mdp_phys";
1001 interrupt-parent = <&mdss>;
1009 clock-names = "iface",
1017 assigned-clocks = <&mmcc MDSS_MDP_CLK>,
1019 assigned-clock-rates = <300000000>,
1025 interconnect-names = "mdp0-mem", "mdp1-mem", "rotator-mem";
1028 #address-cells = <1>;
1029 #size-cells = <0>;
1034 remote-endpoint = <&mdss_hdmi_in>;
1041 remote-endpoint = <&mdss_dsi0_in>;
1048 remote-endpoint = <&mdss_dsi1_in>;
1055 compatible = "qcom,msm8996-dsi-ctrl",
1056 "qcom,mdss-dsi-ctrl";
1058 reg-names = "dsi_ctrl";
1060 interrupt-parent = <&mdss>;
1070 clock-names = "mdp_core",
1077 assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;
1078 assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
1083 #address-cells = <1>;
1084 #size-cells = <0>;
1087 #address-cells = <1>;
1088 #size-cells = <0>;
1093 remote-endpoint = <&mdp5_intf1_out>;
1106 compatible = "qcom,dsi-phy-14nm";
1110 reg-names = "dsi_phy",
1114 #clock-cells = <1>;
1115 #phy-cells = <0>;
1118 clock-names = "iface", "ref";
1123 compatible = "qcom,msm8996-dsi-ctrl",
1124 "qcom,mdss-dsi-ctrl";
1126 reg-names = "dsi_ctrl";
1128 interrupt-parent = <&mdss>;
1138 clock-names = "mdp_core",
1145 assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>;
1146 assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>;
1151 #address-cells = <1>;
1152 #size-cells = <0>;
1155 #address-cells = <1>;
1156 #size-cells = <0>;
1161 remote-endpoint = <&mdp5_intf2_out>;
1174 compatible = "qcom,dsi-phy-14nm";
1178 reg-names = "dsi_phy",
1182 #clock-cells = <1>;
1183 #phy-cells = <0>;
1186 clock-names = "iface", "ref";
1190 mdss_hdmi: hdmi-tx@9a0000 {
1191 compatible = "qcom,hdmi-tx-8996";
1195 reg-names = "core_physical",
1199 interrupt-parent = <&mdss>;
1207 clock-names =
1215 #sound-dai-cells = <1>;
1220 #address-cells = <1>;
1221 #size-cells = <0>;
1226 remote-endpoint = <&mdp5_intf3_out>;
1233 #phy-cells = <0>;
1234 compatible = "qcom,hdmi-phy-8996";
1241 reg-names = "hdmi_pll",
1251 clock-names = "iface",
1255 #clock-cells = <0>;
1262 compatible = "qcom,adreno-530.2", "qcom,adreno";
1265 reg-names = "kgsl_3d0_reg_memory";
1275 clock-names = "core",
1282 interconnect-names = "gfx-mem";
1284 power-domains = <&mmcc GPU_GX_GDSC>;
1287 nvmem-cells = <&speedbin_efuse>;
1288 nvmem-cell-names = "speed_bin";
1290 operating-points-v2 = <&gpu_opp_table>;
1294 #cooling-cells = <2>;
1296 gpu_opp_table: opp-table {
1297 compatible = "operating-points-v2";
1304 opp-624000000 {
1305 opp-hz = /bits/ 64 <624000000>;
1306 opp-supported-hw = <0x09>;
1308 opp-560000000 {
1309 opp-hz = /bits/ 64 <560000000>;
1310 opp-supported-hw = <0x0d>;
1312 opp-510000000 {
1313 opp-hz = /bits/ 64 <510000000>;
1314 opp-supported-hw = <0xff>;
1316 opp-401800000 {
1317 opp-hz = /bits/ 64 <401800000>;
1318 opp-supported-hw = <0xff>;
1320 opp-315000000 {
1321 opp-hz = /bits/ 64 <315000000>;
1322 opp-supported-hw = <0xff>;
1324 opp-214000000 {
1325 opp-hz = /bits/ 64 <214000000>;
1326 opp-supported-hw = <0xff>;
1328 opp-133000000 {
1329 opp-hz = /bits/ 64 <133000000>;
1330 opp-supported-hw = <0xff>;
1334 zap-shader {
1335 memory-region = <&gpu_mem>;
1340 compatible = "qcom,msm8996-pinctrl";
1343 gpio-controller;
1344 gpio-ranges = <&tlmm 0 0 150>;
1345 #gpio-cells = <2>;
1346 interrupt-controller;
1347 #interrupt-cells = <2>;
1349 blsp1_spi1_default: blsp1-spi1-default-state {
1350 spi-pins {
1353 drive-strength = <12>;
1354 bias-disable;
1357 cs-pins {
1360 drive-strength = <16>;
1361 bias-disable;
1362 output-high;
1366 blsp1_spi1_sleep: blsp1-spi1-sleep-state {
1369 drive-strength = <2>;
1370 bias-pull-down;
1373 blsp2_uart2_2pins_default: blsp2-uart2-2pins-state {
1376 drive-strength = <16>;
1377 bias-disable;
1380 blsp2_uart2_2pins_sleep: blsp2-uart2-2pins-sleep-state {
1383 drive-strength = <2>;
1384 bias-disable;
1387 blsp2_i2c2_default: blsp2-i2c2-state {
1390 drive-strength = <16>;
1391 bias-disable;
1394 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
1397 drive-strength = <2>;
1398 bias-disable;
1401 blsp1_i2c6_default: blsp1-i2c6-state {
1404 drive-strength = <16>;
1405 bias-disable;
1408 blsp1_i2c6_sleep: blsp1-i2c6-sleep-state {
1411 drive-strength = <2>;
1412 bias-pull-up;
1415 cci0_default: cci0-default-state {
1418 drive-strength = <16>;
1419 bias-disable;
1423 camera_rear_default: camera-rear-default-state {
1424 camera0_mclk: mclk0-pins {
1427 drive-strength = <16>;
1428 bias-disable;
1431 camera0_rst: rst-pins {
1434 drive-strength = <16>;
1435 bias-disable;
1438 camera0_pwdn: pwdn-pins {
1441 drive-strength = <16>;
1442 bias-disable;
1446 cci1_default: cci1-default-state {
1449 drive-strength = <16>;
1450 bias-disable;
1454 camera_board_default: camera-board-default-state {
1455 mclk1-pins {
1458 drive-strength = <16>;
1459 bias-disable;
1462 pwdn-pins {
1465 drive-strength = <16>;
1466 bias-disable;
1469 rst-pins {
1472 drive-strength = <16>;
1473 bias-disable;
1478 camera_front_default: camera-front-default-state {
1479 camera2_mclk: mclk2-pins {
1482 drive-strength = <16>;
1483 bias-disable;
1486 camera2_rst: rst-pins {
1489 drive-strength = <16>;
1490 bias-disable;
1493 pwdn-pins {
1496 drive-strength = <16>;
1497 bias-disable;
1501 pcie0_state_on: pcie0-state-on-state {
1502 perst-pins {
1505 drive-strength = <2>;
1506 bias-pull-down;
1509 clkreq-pins {
1512 drive-strength = <2>;
1513 bias-pull-up;
1516 wake-pins {
1519 drive-strength = <2>;
1520 bias-pull-up;
1524 pcie0_state_off: pcie0-state-off-state {
1525 perst-pins {
1528 drive-strength = <2>;
1529 bias-pull-down;
1532 clkreq-pins {
1535 drive-strength = <2>;
1536 bias-disable;
1539 wake-pins {
1542 drive-strength = <2>;
1543 bias-disable;
1547 blsp1_uart2_default: blsp1-uart2-default-state {
1550 drive-strength = <16>;
1551 bias-disable;
1554 blsp1_uart2_sleep: blsp1-uart2-sleep-state {
1557 drive-strength = <2>;
1558 bias-disable;
1561 blsp1_i2c3_default: blsp1-i2c3-default-state {
1564 drive-strength = <16>;
1565 bias-disable;
1568 blsp1_i2c3_sleep: blsp1-i2c3-sleep-state {
1571 drive-strength = <2>;
1572 bias-disable;
1575 blsp2_uart3_4pins_default: blsp2-uart3-4pins-state {
1578 drive-strength = <16>;
1579 bias-disable;
1582 blsp2_uart3_4pins_sleep: blsp2-uart3-4pins-sleep-state {
1585 drive-strength = <2>;
1586 bias-disable;
1589 blsp2_i2c3_default: blsp2-i2c3-state-state {
1592 drive-strength = <16>;
1593 bias-disable;
1596 blsp2_i2c3_sleep: blsp2-i2c3-sleep-state {
1599 drive-strength = <2>;
1600 bias-disable;
1603 wcd_intr_default: wcd-intr-default-state {
1606 drive-strength = <2>;
1607 bias-pull-down;
1610 blsp2_i2c1_default: blsp2-i2c1-state {
1613 drive-strength = <16>;
1614 bias-disable;
1617 blsp2_i2c1_sleep: blsp2-i2c1-sleep-state {
1620 drive-strength = <2>;
1621 bias-disable;
1624 blsp2_i2c5_default: blsp2-i2c5-state {
1627 drive-strength = <2>;
1628 bias-disable;
1633 cdc_reset_active: cdc-reset-active-state {
1636 drive-strength = <16>;
1637 bias-pull-down;
1638 output-high;
1641 cdc_reset_sleep: cdc-reset-sleep-state {
1644 drive-strength = <16>;
1645 bias-disable;
1646 output-low;
1649 blsp2_spi6_default: blsp2-spi6-default-state {
1650 spi-pins {
1653 drive-strength = <12>;
1654 bias-disable;
1657 cs-pins {
1660 drive-strength = <16>;
1661 bias-disable;
1662 output-high;
1666 blsp2_spi6_sleep: blsp2-spi6-sleep-state {
1669 drive-strength = <2>;
1670 bias-pull-down;
1673 blsp2_i2c6_default: blsp2-i2c6-state {
1676 drive-strength = <16>;
1677 bias-disable;
1680 blsp2_i2c6_sleep: blsp2-i2c6-sleep-state {
1683 drive-strength = <2>;
1684 bias-disable;
1687 pcie1_state_on: pcie1-on-state {
1688 perst-pins {
1691 drive-strength = <2>;
1692 bias-pull-down;
1695 clkreq-pins {
1698 drive-strength = <2>;
1699 bias-pull-up;
1702 wake-pins {
1705 drive-strength = <2>;
1706 bias-pull-down;
1710 pcie1_state_off: pcie1-off-state {
1712 clkreq-pins {
1715 drive-strength = <2>;
1716 bias-disable;
1719 wake-pins {
1722 drive-strength = <2>;
1723 bias-disable;
1727 pcie2_state_on: pcie2-on-state {
1728 perst-pins {
1731 drive-strength = <2>;
1732 bias-pull-down;
1735 clkreq-pins {
1738 drive-strength = <2>;
1739 bias-pull-up;
1742 wake-pins {
1745 drive-strength = <2>;
1746 bias-pull-down;
1750 pcie2_state_off: pcie2-off-state {
1752 clkreq-pins {
1755 drive-strength = <2>;
1756 bias-disable;
1759 wake-pins {
1762 drive-strength = <2>;
1763 bias-disable;
1767 sdc1_state_on: sdc1-on-state {
1768 clk-pins {
1770 bias-disable;
1771 drive-strength = <16>;
1774 cmd-pins {
1776 bias-pull-up;
1777 drive-strength = <10>;
1780 data-pins {
1782 bias-pull-up;
1783 drive-strength = <10>;
1786 rclk-pins {
1788 bias-pull-down;
1792 sdc1_state_off: sdc1-off-state {
1793 clk-pins {
1795 bias-disable;
1796 drive-strength = <2>;
1799 cmd-pins {
1801 bias-pull-up;
1802 drive-strength = <2>;
1805 data-pins {
1807 bias-pull-up;
1808 drive-strength = <2>;
1811 rclk-pins {
1813 bias-pull-down;
1817 sdc2_state_on: sdc2-on-state {
1818 clk-pins {
1820 bias-disable;
1821 drive-strength = <16>;
1824 cmd-pins {
1826 bias-pull-up;
1827 drive-strength = <10>;
1830 data-pins {
1832 bias-pull-up;
1833 drive-strength = <10>;
1837 sdc2_state_off: sdc2-off-state {
1838 clk-pins {
1840 bias-disable;
1841 drive-strength = <2>;
1844 cmd-pins {
1846 bias-pull-up;
1847 drive-strength = <2>;
1850 data-pins {
1852 bias-pull-up;
1853 drive-strength = <2>;
1859 compatible = "qcom,rpm-stats";
1864 compatible = "qcom,spmi-pmic-arb";
1870 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
1871 interrupt-names = "periph_irq";
1875 #address-cells = <2>;
1876 #size-cells = <0>;
1877 interrupt-controller;
1878 #interrupt-cells = <4>;
1882 power-domains = <&gcc AGGRE0_NOC_GDSC>;
1883 compatible = "simple-pm-bus";
1884 #address-cells = <1>;
1885 #size-cells = <1>;
1889 compatible = "qcom,pcie-msm8996";
1891 power-domains = <&gcc PCIE0_GDSC>;
1892 bus-range = <0x00 0xff>;
1893 num-lanes = <1>;
1899 reg-names = "parf", "dbi", "elbi","config";
1902 phy-names = "pciephy";
1904 #address-cells = <3>;
1905 #size-cells = <2>;
1912 interrupt-names = "msi";
1913 #interrupt-cells = <1>;
1914 interrupt-map-mask = <0 0 0 0x7>;
1915 interrupt-map = <0 0 0 1 &intc 0 244 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1920 pinctrl-names = "default", "sleep";
1921 pinctrl-0 = <&pcie0_state_on>;
1922 pinctrl-1 = <&pcie0_state_off>;
1924 linux,pci-domain = <0>;
1932 clock-names = "pipe",
1940 compatible = "qcom,pcie-msm8996";
1941 power-domains = <&gcc PCIE1_GDSC>;
1942 bus-range = <0x00 0xff>;
1943 num-lanes = <1>;
1952 reg-names = "parf", "dbi", "elbi","config";
1955 phy-names = "pciephy";
1957 #address-cells = <3>;
1958 #size-cells = <2>;
1965 interrupt-names = "msi";
1966 #interrupt-cells = <1>;
1967 interrupt-map-mask = <0 0 0 0x7>;
1968 interrupt-map = <0 0 0 1 &intc 0 272 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1973 pinctrl-names = "default", "sleep";
1974 pinctrl-0 = <&pcie1_state_on>;
1975 pinctrl-1 = <&pcie1_state_off>;
1977 linux,pci-domain = <1>;
1985 clock-names = "pipe",
1993 compatible = "qcom,pcie-msm8996";
1994 power-domains = <&gcc PCIE2_GDSC>;
1995 bus-range = <0x00 0xff>;
1996 num-lanes = <1>;
2003 reg-names = "parf", "dbi", "elbi","config";
2006 phy-names = "pciephy";
2008 #address-cells = <3>;
2009 #size-cells = <2>;
2016 interrupt-names = "msi";
2017 #interrupt-cells = <1>;
2018 interrupt-map-mask = <0 0 0 0x7>;
2019 interrupt-map = <0 0 0 1 &intc 0 142 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
2024 pinctrl-names = "default", "sleep";
2025 pinctrl-0 = <&pcie2_state_on>;
2026 pinctrl-1 = <&pcie2_state_off>;
2028 linux,pci-domain = <2>;
2035 clock-names = "pipe",
2044 compatible = "qcom,msm8996-ufshc", "qcom,ufshc",
2045 "jedec,ufs-2.0";
2050 phy-names = "ufsphy";
2052 power-domains = <&gcc UFS_GDSC>;
2054 clock-names =
2078 freq-table-hz =
2093 interconnect-names = "ufs-ddr", "cpu-ufs";
2095 lanes-per-direction = <1>;
2096 #reset-cells = <1>;
2101 compatible = "qcom,msm8996-qmp-ufs-phy";
2103 #address-cells = <1>;
2104 #size-cells = <1>;
2108 clock-names = "ref";
2111 reset-names = "ufsphy";
2118 #clock-cells = <1>;
2119 #phy-cells = <0>;
2124 compatible = "qcom,msm8996-camss";
2139 reg-names = "csiphy0",
2163 interrupt-names = "csiphy0",
2173 power-domains = <&mmcc VFE0_GDSC>,
2211 clock-names = "top_ahb",
2253 #address-cells = <1>;
2254 #size-cells = <0>;
2259 compatible = "qcom,msm8996-cci";
2260 #address-cells = <1>;
2261 #size-cells = <0>;
2264 power-domains = <&mmcc CAMSS_GDSC>;
2269 clock-names = "camss_top_ahb",
2273 assigned-clocks = <&mmcc CAMSS_CCI_AHB_CLK>,
2275 assigned-clock-rates = <80000000>, <37500000>;
2276 pinctrl-names = "default";
2277 pinctrl-0 = <&cci0_default &cci1_default>;
2280 cci_i2c0: i2c-bus@0 {
2282 clock-frequency = <400000>;
2283 #address-cells = <1>;
2284 #size-cells = <0>;
2287 cci_i2c1: i2c-bus@1 {
2289 clock-frequency = <400000>;
2290 #address-cells = <1>;
2291 #size-cells = <0>;
2296 compatible = "qcom,msm8996-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2299 #global-interrupts = <1>;
2303 #iommu-cells = <1>;
2307 clock-names = "bus", "iface";
2309 power-domains = <&mmcc GPU_GDSC>;
2312 venus: video-codec@c00000 {
2313 compatible = "qcom,msm8996-venus";
2316 power-domains = <&mmcc VENUS_GDSC>;
2321 clock-names = "core", "iface", "bus", "mbus";
2324 interconnect-names = "video-mem", "cpu-cfg";
2345 memory-region = <&venus_mem>;
2348 video-decoder {
2349 compatible = "venus-decoder";
2351 clock-names = "core";
2352 power-domains = <&mmcc VENUS_CORE0_GDSC>;
2355 video-encoder {
2356 compatible = "venus-encoder";
2358 clock-names = "core";
2359 power-domains = <&mmcc VENUS_CORE1_GDSC>;
2364 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2367 #global-interrupts = <1>;
2371 #iommu-cells = <1>;
2374 clock-names = "bus", "iface";
2376 power-domains = <&mmcc MDSS_GDSC>;
2380 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2382 #global-interrupts = <1>;
2391 power-domains = <&mmcc MMAGIC_VIDEO_GDSC>;
2394 clock-names = "bus", "iface";
2395 #iommu-cells = <1>;
2400 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2403 #global-interrupts = <1>;
2407 power-domains = <&mmcc MMAGIC_CAMSS_GDSC>;
2410 clock-names = "bus", "iface";
2411 #iommu-cells = <1>;
2415 compatible = "qcom,msm8996-smmu-v2", "qcom,smmu-v2";
2417 #iommu-cells = <1>;
2418 power-domains = <&gcc HLOS1_VOTE_LPASS_CORE_GDSC>;
2420 #global-interrupts = <1>;
2437 clock-names = "bus", "iface";
2441 compatible = "qcom,msm8996-slpi-pil";
2444 interrupts-extended = <&intc 0 390 IRQ_TYPE_EDGE_RISING>,
2449 interrupt-names = "wdog",
2453 "stop-ack";
2457 clock-names = "xo", "aggre2";
2459 memory-region = <&slpi_mem>;
2461 qcom,smem-states = <&slpi_smp2p_out 0>;
2462 qcom,smem-state-names = "stop";
2464 power-domains = <&rpmpd MSM8996_VDDSSCX>;
2465 power-domain-names = "ssc_cx";
2469 smd-edge {
2474 qcom,smd-edge = <3>;
2475 qcom,remote-pid = <3>;
2480 compatible = "qcom,msm8996-mss-pil";
2483 reg-names = "qdsp6", "rmb";
2485 interrupts-extended = <&intc 0 448 IRQ_TYPE_EDGE_RISING>,
2491 interrupt-names = "wdog", "fatal", "ready",
2492 "handover", "stop-ack",
2493 "shutdown-ack";
2504 clock-names = "iface", "bus", "mem", "xo", "gpll0_mss",
2508 reset-names = "mss_restart";
2510 power-domains = <&rpmpd MSM8996_VDDCX>,
2512 power-domain-names = "cx", "mx";
2514 qcom,smem-states = <&mpss_smp2p_out 0>;
2515 qcom,smem-state-names = "stop";
2517 qcom,halt-regs = <&tcsr_1 0x3000 0x5000 0x4000>;
2522 memory-region = <&mba_mem>;
2526 memory-region = <&mpss_mem>;
2530 memory-region = <&mdata_mem>;
2533 smd-edge {
2538 qcom,smd-edge = <0>;
2539 qcom,remote-pid = <1>;
2544 compatible = "arm,coresight-stm", "arm,primecell";
2547 reg-names = "stm-base", "stm-stimulus-base";
2550 clock-names = "apb_pclk", "atclk";
2552 out-ports {
2555 remote-endpoint =
2563 compatible = "arm,coresight-tpiu", "arm,primecell";
2567 clock-names = "apb_pclk", "atclk";
2569 in-ports {
2572 remote-endpoint =
2580 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2584 clock-names = "apb_pclk", "atclk";
2586 in-ports {
2587 #address-cells = <1>;
2588 #size-cells = <0>;
2593 remote-endpoint =
2599 out-ports {
2602 remote-endpoint =
2610 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2614 clock-names = "apb_pclk", "atclk";
2616 in-ports {
2617 #address-cells = <1>;
2618 #size-cells = <0>;
2623 remote-endpoint =
2629 out-ports {
2632 remote-endpoint =
2640 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2644 clock-names = "apb_pclk", "atclk";
2647 out-ports {
2650 remote-endpoint =
2658 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2662 clock-names = "apb_pclk", "atclk";
2664 in-ports {
2665 #address-cells = <1>;
2666 #size-cells = <0>;
2671 remote-endpoint =
2679 remote-endpoint =
2687 remote-endpoint =
2693 out-ports {
2696 remote-endpoint =
2704 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2708 clock-names = "apb_pclk", "atclk";
2710 in-ports {
2713 remote-endpoint =
2719 out-ports {
2720 #address-cells = <1>;
2721 #size-cells = <0>;
2726 remote-endpoint =
2734 remote-endpoint =
2742 compatible = "arm,coresight-tmc", "arm,primecell";
2746 clock-names = "apb_pclk", "atclk";
2748 in-ports {
2751 remote-endpoint =
2757 out-ports {
2760 remote-endpoint =
2768 compatible = "arm,coresight-tmc", "arm,primecell";
2772 clock-names = "apb_pclk", "atclk";
2773 arm,scatter-gather;
2775 in-ports {
2778 remote-endpoint =
2786 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2790 clock-names = "apb_pclk";
2796 compatible = "arm,coresight-etm4x", "arm,primecell";
2800 clock-names = "apb_pclk", "atclk";
2804 out-ports {
2807 remote-endpoint =
2815 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2819 clock-names = "apb_pclk";
2825 compatible = "arm,coresight-etm4x", "arm,primecell";
2829 clock-names = "apb_pclk", "atclk";
2833 out-ports {
2836 remote-endpoint =
2844 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2848 clock-names = "apb_pclk", "atclk";
2850 in-ports {
2851 #address-cells = <1>;
2852 #size-cells = <0>;
2857 remote-endpoint = <&etm0_out>;
2864 remote-endpoint = <&etm1_out>;
2869 out-ports {
2872 remote-endpoint =
2880 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2884 clock-names = "apb_pclk";
2890 compatible = "arm,coresight-etm4x", "arm,primecell";
2894 clock-names = "apb_pclk", "atclk";
2898 out-ports {
2901 remote-endpoint =
2909 compatible = "arm,coresight-cpu-debug", "arm,primecell";
2913 clock-names = "apb_pclk";
2919 compatible = "arm,coresight-etm4x", "arm,primecell";
2923 clock-names = "apb_pclk", "atclk";
2927 out-ports {
2930 remote-endpoint =
2938 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2942 clock-names = "apb_pclk", "atclk";
2944 in-ports {
2945 #address-cells = <1>;
2946 #size-cells = <0>;
2951 remote-endpoint = <&etm2_out>;
2958 remote-endpoint = <&etm3_out>;
2963 out-ports {
2966 remote-endpoint =
2974 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2978 clock-names = "apb_pclk", "atclk";
2980 in-ports {
2981 #address-cells = <1>;
2982 #size-cells = <0>;
2987 remote-endpoint =
2995 remote-endpoint =
3001 out-ports {
3004 remote-endpoint =
3011 kryocc: clock-controller@6400000 {
3012 compatible = "qcom,msm8996-apcc";
3015 clock-names = "xo", "sys_apcs_aux";
3018 #clock-cells = <1>;
3022 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3024 #address-cells = <1>;
3025 #size-cells = <1>;
3030 interrupt-names = "hs_phy_irq", "ss_phy_irq";
3037 clock-names = "cfg_noc",
3043 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
3045 assigned-clock-rates = <19200000>, <120000000>;
3049 interconnect-names = "usb-ddr", "apps-usb";
3051 power-domains = <&gcc USB30_GDSC>;
3059 phy-names = "usb2-phy", "usb3-phy";
3060 snps,hird-threshold = /bits/ 8 <0>;
3063 snps,is-utmi-l1-suspend;
3064 tx-fifo-resize;
3069 compatible = "qcom,msm8996-qmp-usb3-phy";
3071 #address-cells = <1>;
3072 #size-cells = <1>;
3078 clock-names = "aux", "cfg_ahb", "ref";
3082 reset-names = "phy", "common";
3089 #phy-cells = <0>;
3091 #clock-cells = <0>;
3092 clock-output-names = "usb3_phy_pipe_clk_src";
3094 clock-names = "pipe0";
3099 compatible = "qcom,msm8996-qusb2-phy";
3101 #phy-cells = <0>;
3105 clock-names = "cfg_ahb", "ref";
3108 nvmem-cells = <&qusb2p_hstx_trim>;
3113 compatible = "qcom,msm8996-qusb2-phy";
3115 #phy-cells = <0>;
3119 clock-names = "cfg_ahb", "ref";
3122 nvmem-cells = <&qusb2s_hstx_trim>;
3127 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3129 reg-names = "hc", "core";
3133 interrupt-names = "hc_irq", "pwr_irq";
3135 clock-names = "iface", "core", "xo";
3141 pinctrl-names = "default", "sleep";
3142 pinctrl-0 = <&sdc1_state_on>;
3143 pinctrl-1 = <&sdc1_state_off>;
3145 bus-width = <8>;
3146 non-removable;
3151 compatible = "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4";
3153 reg-names = "hc", "core";
3157 interrupt-names = "hc_irq", "pwr_irq";
3159 clock-names = "iface", "core", "xo";
3165 pinctrl-names = "default", "sleep";
3166 pinctrl-0 = <&sdc2_state_on>;
3167 pinctrl-1 = <&sdc2_state_off>;
3169 bus-width = <4>;
3173 blsp1_dma: dma-controller@7544000 {
3174 compatible = "qcom,bam-v1.7.0";
3178 clock-names = "bam_clk";
3179 qcom,controlled-remotely;
3180 #dma-cells = <1>;
3185 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3190 clock-names = "core", "iface";
3191 pinctrl-names = "default", "sleep";
3192 pinctrl-0 = <&blsp1_uart2_default>;
3193 pinctrl-1 = <&blsp1_uart2_sleep>;
3195 dma-names = "tx", "rx";
3200 compatible = "qcom,spi-qup-v2.2.1";
3205 clock-names = "core", "iface";
3206 pinctrl-names = "default", "sleep";
3207 pinctrl-0 = <&blsp1_spi1_default>;
3208 pinctrl-1 = <&blsp1_spi1_sleep>;
3210 dma-names = "tx", "rx";
3211 #address-cells = <1>;
3212 #size-cells = <0>;
3217 compatible = "qcom,i2c-qup-v2.2.1";
3222 clock-names = "core", "iface";
3223 pinctrl-names = "default", "sleep";
3224 pinctrl-0 = <&blsp1_i2c3_default>;
3225 pinctrl-1 = <&blsp1_i2c3_sleep>;
3227 dma-names = "tx", "rx";
3228 #address-cells = <1>;
3229 #size-cells = <0>;
3234 compatible = "qcom,i2c-qup-v2.2.1";
3239 clock-names = "core", "iface";
3240 pinctrl-names = "default", "sleep";
3241 pinctrl-0 = <&blsp1_i2c6_default>;
3242 pinctrl-1 = <&blsp1_i2c6_sleep>;
3244 dma-names = "tx", "rx";
3245 #address-cells = <1>;
3246 #size-cells = <0>;
3250 blsp2_dma: dma-controller@7584000 {
3251 compatible = "qcom,bam-v1.7.0";
3255 clock-names = "bam_clk";
3256 qcom,controlled-remotely;
3257 #dma-cells = <1>;
3262 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3267 clock-names = "core", "iface";
3272 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
3277 clock-names = "core", "iface";
3282 compatible = "qcom,i2c-qup-v2.2.1";
3287 clock-names = "core", "iface";
3288 pinctrl-names = "default", "sleep";
3289 pinctrl-0 = <&blsp2_i2c1_default>;
3290 pinctrl-1 = <&blsp2_i2c1_sleep>;
3292 dma-names = "tx", "rx";
3293 #address-cells = <1>;
3294 #size-cells = <0>;
3299 compatible = "qcom,i2c-qup-v2.2.1";
3304 clock-names = "core", "iface";
3305 pinctrl-names = "default", "sleep";
3306 pinctrl-0 = <&blsp2_i2c2_default>;
3307 pinctrl-1 = <&blsp2_i2c2_sleep>;
3309 dma-names = "tx", "rx";
3310 #address-cells = <1>;
3311 #size-cells = <0>;
3316 compatible = "qcom,i2c-qup-v2.2.1";
3321 clock-names = "core", "iface";
3322 clock-frequency = <400000>;
3323 pinctrl-names = "default", "sleep";
3324 pinctrl-0 = <&blsp2_i2c3_default>;
3325 pinctrl-1 = <&blsp2_i2c3_sleep>;
3327 dma-names = "tx", "rx";
3328 #address-cells = <1>;
3329 #size-cells = <0>;
3334 compatible = "qcom,i2c-qup-v2.2.1";
3339 clock-names = "core", "iface";
3340 pinctrl-names = "default";
3341 pinctrl-0 = <&blsp2_i2c5_default>;
3343 dma-names = "tx", "rx";
3344 #address-cells = <1>;
3345 #size-cells = <0>;
3350 compatible = "qcom,i2c-qup-v2.2.1";
3355 clock-names = "core", "iface";
3356 pinctrl-names = "default", "sleep";
3357 pinctrl-0 = <&blsp2_i2c6_default>;
3358 pinctrl-1 = <&blsp2_i2c6_sleep>;
3360 dma-names = "tx", "rx";
3361 #address-cells = <1>;
3362 #size-cells = <0>;
3367 compatible = "qcom,spi-qup-v2.2.1";
3372 clock-names = "core", "iface";
3373 pinctrl-names = "default", "sleep";
3374 pinctrl-0 = <&blsp2_spi6_default>;
3375 pinctrl-1 = <&blsp2_spi6_sleep>;
3377 dma-names = "tx", "rx";
3378 #address-cells = <1>;
3379 #size-cells = <0>;
3384 compatible = "qcom,msm8996-dwc3", "qcom,dwc3";
3386 #address-cells = <1>;
3387 #size-cells = <1>;
3391 interrupt-names = "hs_phy_irq";
3398 clock-names = "cfg_noc",
3404 assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
3406 assigned-clock-rates = <19200000>, <60000000>;
3408 power-domains = <&gcc USB30_GDSC>;
3409 qcom,select-utmi-as-pipe-clk;
3417 phy-names = "usb2-phy";
3418 maximum-speed = "high-speed";
3424 slimbam: dma-controller@9184000 {
3425 compatible = "qcom,bam-v1.7.0";
3426 qcom,controlled-remotely;
3428 num-channels = <31>;
3430 #dma-cells = <1>;
3432 qcom,num-ees = <2>;
3435 slim_msm: slim-ngd@91c0000 {
3436 compatible = "qcom,slim-ngd-v1.5.0";
3440 dma-names = "rx", "tx";
3441 #address-cells = <1>;
3442 #size-cells = <0>;
3448 compatible = "qcom,msm8996-adsp-pil";
3451 interrupts-extended = <&intc 0 162 IRQ_TYPE_EDGE_RISING>,
3456 interrupt-names = "wdog", "fatal", "ready",
3457 "handover", "stop-ack";
3460 clock-names = "xo";
3462 memory-region = <&adsp_mem>;
3464 qcom,smem-states = <&adsp_smp2p_out 0>;
3465 qcom,smem-state-names = "stop";
3467 power-domains = <&rpmpd MSM8996_VDDCX>;
3468 power-domain-names = "cx";
3472 smd-edge {
3477 qcom,smd-edge = <1>;
3478 qcom,remote-pid = <2>;
3481 power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
3482 compatible = "qcom,apr-v2";
3483 qcom,smd-channels = "apr_audio_svc";
3485 #address-cells = <1>;
3486 #size-cells = <0>;
3497 compatible = "qcom,q6afe-dais";
3498 #address-cells = <1>;
3499 #size-cells = <0>;
3500 #sound-dai-cells = <1>;
3511 compatible = "qcom,q6asm-dais";
3512 #address-cells = <1>;
3513 #size-cells = <0>;
3514 #sound-dai-cells = <1>;
3523 compatible = "qcom,q6adm-routing";
3524 #sound-dai-cells = <0>;
3532 compatible = "qcom,msm8996-apcs-hmss-global";
3535 #mbox-cells = <1>;
3536 #clock-cells = <0>;
3540 #address-cells = <1>;
3541 #size-cells = <1>;
3543 compatible = "arm,armv7-timer-mem";
3545 clock-frequency = <19200000>;
3548 frame-number = <0>;
3556 frame-number = <1>;
3563 frame-number = <2>;
3570 frame-number = <3>;
3577 frame-number = <4>;
3584 frame-number = <5>;
3591 frame-number = <6>;
3603 cbf: clock-controller@9a11000 {
3604 compatible = "qcom,msm8996-cbf";
3607 #clock-cells = <0>;
3608 #interconnect-cells = <1>;
3611 intc: interrupt-controller@9bc0000 {
3612 compatible = "qcom,msm8996-gic-v3", "arm,gic-v3";
3613 #interrupt-cells = <3>;
3614 interrupt-controller;
3615 #redistributor-regions = <1>;
3616 redistributor-stride = <0x0 0x40000>;
3626 thermal-zones {
3627 cpu0-thermal {
3628 polling-delay-passive = <250>;
3629 polling-delay = <1000>;
3631 thermal-sensors = <&tsens0 3>;
3634 cpu0_alert0: trip-point0 {
3640 cpu0_crit: cpu-crit {
3648 cpu1-thermal {
3649 polling-delay-passive = <250>;
3650 polling-delay = <1000>;
3652 thermal-sensors = <&tsens0 5>;
3655 cpu1_alert0: trip-point0 {
3661 cpu1_crit: cpu-crit {
3669 cpu2-thermal {
3670 polling-delay-passive = <250>;
3671 polling-delay = <1000>;
3673 thermal-sensors = <&tsens0 8>;
3676 cpu2_alert0: trip-point0 {
3682 cpu2_crit: cpu-crit {
3690 cpu3-thermal {
3691 polling-delay-passive = <250>;
3692 polling-delay = <1000>;
3694 thermal-sensors = <&tsens0 10>;
3697 cpu3_alert0: trip-point0 {
3703 cpu3_crit: cpu-crit {
3711 gpu-top-thermal {
3712 polling-delay-passive = <250>;
3713 polling-delay = <1000>;
3715 thermal-sensors = <&tsens1 6>;
3718 gpu1_alert0: trip-point0 {
3725 cooling-maps {
3728 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3733 gpu-bottom-thermal {
3734 polling-delay-passive = <250>;
3735 polling-delay = <1000>;
3737 thermal-sensors = <&tsens1 7>;
3740 gpu2_alert0: trip-point0 {
3747 cooling-maps {
3750 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3755 m4m-thermal {
3756 polling-delay-passive = <250>;
3757 polling-delay = <1000>;
3759 thermal-sensors = <&tsens0 1>;
3762 m4m_alert0: trip-point0 {
3770 l3-or-venus-thermal {
3771 polling-delay-passive = <250>;
3772 polling-delay = <1000>;
3774 thermal-sensors = <&tsens0 2>;
3777 l3_or_venus_alert0: trip-point0 {
3785 cluster0-l2-thermal {
3786 polling-delay-passive = <250>;
3787 polling-delay = <1000>;
3789 thermal-sensors = <&tsens0 7>;
3792 cluster0_l2_alert0: trip-point0 {
3800 cluster1-l2-thermal {
3801 polling-delay-passive = <250>;
3802 polling-delay = <1000>;
3804 thermal-sensors = <&tsens0 12>;
3807 cluster1_l2_alert0: trip-point0 {
3815 camera-thermal {
3816 polling-delay-passive = <250>;
3817 polling-delay = <1000>;
3819 thermal-sensors = <&tsens1 1>;
3822 camera_alert0: trip-point0 {
3830 q6-dsp-thermal {
3831 polling-delay-passive = <250>;
3832 polling-delay = <1000>;
3834 thermal-sensors = <&tsens1 2>;
3837 q6_dsp_alert0: trip-point0 {
3845 mem-thermal {
3846 polling-delay-passive = <250>;
3847 polling-delay = <1000>;
3849 thermal-sensors = <&tsens1 3>;
3852 mem_alert0: trip-point0 {
3860 modemtx-thermal {
3861 polling-delay-passive = <250>;
3862 polling-delay = <1000>;
3864 thermal-sensors = <&tsens1 4>;
3867 modemtx_alert0: trip-point0 {
3877 compatible = "arm,armv8-timer";