Lines Matching +full:polling +full:- +full:delay +full:- +full:passive
1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2016-2022, AngeloGioacchino Del Regno
9 #include <dt-bindings/clock/qcom,gcc-msm8976.h>
10 #include <dt-bindings/clock/qcom,rpmcc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/interrupt-controller/irq.h>
14 #include <dt-bindings/power/qcom-rpmpd.h>
17 interrupt-parent = <&intc>;
18 #address-cells = <2>;
19 #size-cells = <2>;
24 xo_board: xo-board {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
31 #address-cells = <1>;
32 #size-cells = <0>;
36 compatible = "arm,cortex-a53";
38 enable-method = "psci";
39 cpu-idle-states = <&little_cpu_sleep_0>;
40 capacity-dmips-mhz = <573>;
41 next-level-cache = <&l2_0>;
42 #cooling-cells = <2>;
47 compatible = "arm,cortex-a53";
49 enable-method = "psci";
50 cpu-idle-states = <&little_cpu_sleep_0>;
51 capacity-dmips-mhz = <573>;
52 next-level-cache = <&l2_0>;
53 #cooling-cells = <2>;
58 compatible = "arm,cortex-a53";
60 enable-method = "psci";
61 cpu-idle-states = <&little_cpu_sleep_0>;
62 capacity-dmips-mhz = <573>;
63 next-level-cache = <&l2_0>;
64 #cooling-cells = <2>;
69 compatible = "arm,cortex-a53";
71 enable-method = "psci";
72 cpu-idle-states = <&little_cpu_sleep_0>;
73 capacity-dmips-mhz = <573>;
74 next-level-cache = <&l2_0>;
75 #cooling-cells = <2>;
80 compatible = "arm,cortex-a72";
82 enable-method = "psci";
83 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
84 capacity-dmips-mhz = <1024>;
85 next-level-cache = <&l2_1>;
86 #cooling-cells = <2>;
91 compatible = "arm,cortex-a72";
93 enable-method = "psci";
94 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
95 capacity-dmips-mhz = <1024>;
96 next-level-cache = <&l2_1>;
97 #cooling-cells = <2>;
102 compatible = "arm,cortex-a72";
104 enable-method = "psci";
105 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
106 capacity-dmips-mhz = <1024>;
107 next-level-cache = <&l2_1>;
108 #cooling-cells = <2>;
113 compatible = "arm,cortex-a72";
115 enable-method = "psci";
116 cpu-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>;
117 capacity-dmips-mhz = <1024>;
118 next-level-cache = <&l2_1>;
119 #cooling-cells = <2>;
122 cpu-map {
160 idle-states {
161 entry-method = "psci";
163 little_cpu_sleep_0: cpu-sleep-0-0 {
164 compatible = "arm,idle-state";
165 idle-state-name = "little-power-collapse";
166 arm,psci-suspend-param = <0x40000003>;
167 entry-latency-us = <181>;
168 exit-latency-us = <149>;
169 min-residency-us = <703>;
170 local-timer-stop;
173 big_cpu_sleep_0: cpu-sleep-1-0 {
174 compatible = "arm,idle-state";
175 idle-state-name = "big-retention";
176 arm,psci-suspend-param = <0x00000002>;
177 entry-latency-us = <142>;
178 exit-latency-us = <99>;
179 min-residency-us = <242>;
182 big_cpu_sleep_1: cpu-sleep-1-1 {
183 compatible = "arm,idle-state";
184 idle-state-name = "big-power-collapse";
185 arm,psci-suspend-param = <0x40000003>;
186 entry-latency-us = <158>;
187 exit-latency-us = <144>;
188 min-residency-us = <863>;
189 local-timer-stop;
193 l2_0: l2-cache0 {
195 cache-level = <2>;
196 cache-unified;
199 l2_1: l2-cache1 {
201 cache-level = <2>;
202 cache-unified;
208 compatible = "qcom,scm-msm8976", "qcom,scm";
212 clock-names = "core", "bus", "iface";
213 #reset-cells = <1>;
215 qcom,dload-mode = <&tcsr 0x6100>;
226 compatible = "arm,armv8-pmuv3";
231 compatible = "arm,psci-1.0";
236 compatible = "qcom,msm8976-rpm-proc", "qcom,rpm-proc";
238 smd-edge {
241 qcom,smd-edge = <15>;
243 rpm_requests: rpm-requests {
244 compatible = "qcom,rpm-msm8976";
245 qcom,smd-channels = "rpm_requests";
247 rpmcc: clock-controller {
248 compatible = "qcom,rpmcc-msm8976", "qcom,rpmcc";
250 clock-names = "xo";
251 #clock-cells = <1>;
254 rpmpd: power-controller {
255 compatible = "qcom,msm8976-rpmpd";
256 #power-domain-cells = <1>;
257 operating-points-v2 = <&rpmpd_opp_table>;
259 rpmpd_opp_table: opp-table {
260 compatible = "operating-points-v2";
263 opp-level = <RPM_SMD_LEVEL_RETENTION>;
267 opp-level = <RPM_SMD_LEVEL_RETENTION_PLUS>;
271 opp-level = <RPM_SMD_LEVEL_MIN_SVS>;
275 opp-level = <RPM_SMD_LEVEL_LOW_SVS>;
279 opp-level = <RPM_SMD_LEVEL_SVS>;
283 opp-level = <RPM_SMD_LEVEL_SVS_PLUS>;
287 opp-level = <RPM_SMD_LEVEL_NOM>;
291 opp-level = <RPM_SMD_LEVEL_NOM_PLUS>;
295 opp-level = <RPM_SMD_LEVEL_TURBO>;
299 opp-level = <RPM_SMD_LEVEL_TURBO_NO_CPR>;
303 opp-level = <RPM_SMD_LEVEL_TURBO_HIGH>;
311 reserved-memory {
312 #address-cells = <2>;
313 #size-cells = <2>;
316 ext-region@85b00000 {
318 no-map;
324 no-map;
327 qcom,rpm-msg-ram = <&rpm_msg_ram>;
332 no-map;
337 no-map;
342 no-map;
347 no-map;
350 tz-apps@8dd00000 {
352 no-map;
356 smp2p-hexagon {
361 qcom,local-pid = <0>;
362 qcom,remote-pid = <2>;
365 adsp_smp2p_out: master-kernel {
366 qcom,entry-name = "master-kernel";
368 #qcom,smem-state-cells = <1>;
371 adsp_smp2p_in: slave-kernel {
372 qcom,entry-name = "slave-kernel";
374 interrupt-controller;
375 #interrupt-cells = <2>;
379 smp2p-modem {
384 qcom,local-pid = <0>;
385 qcom,remote-pid = <1>;
388 modem_smp2p_out: master-kernel {
389 qcom,entry-name = "master-kernel";
391 #qcom,smem-state-cells = <1>;
394 modem_smp2p_in: slave-kernel {
395 qcom,entry-name = "slave-kernel";
397 interrupt-controller;
398 #interrupt-cells = <2>;
402 smp2p-wcnss {
407 qcom,local-pid = <0>;
408 qcom,remote-pid = <4>;
411 wcnss_smp2p_out: master-kernel {
412 qcom,entry-name = "master-kernel";
414 #qcom,smem-state-cells = <1>;
417 wcnss_smp2p_in: slave-kernel {
418 qcom,entry-name = "slave-kernel";
420 interrupt-controller;
421 #interrupt-cells = <2>;
428 #address-cells = <1>;
429 #size-cells = <0>;
431 qcom,ipc-1 = <&apcs 8 12>;
432 qcom,ipc-2 = <&apcs 8 9>;
433 qcom,ipc-3 = <&apcs 8 18>;
437 #qcom,smem-state-cells = <1>;
444 interrupt-controller;
445 #interrupt-cells = <2>;
452 interrupt-controller;
453 #interrupt-cells = <2>;
458 #address-cells = <1>;
459 #size-cells = <1>;
461 compatible = "simple-bus";
467 clock-names = "core";
471 compatible = "qcom,rpm-msg-ram";
476 compatible = "qcom,usb-hs-28nm-femtophy";
478 #phy-cells = <0>;
482 clock-names = "ref", "ahb", "sleep";
485 reset-names = "phy", "por";
490 compatible = "qcom,msm8976-qfprom", "qcom,qfprom";
492 #address-cells = <1>;
493 #size-cells = <1>;
500 tsens_s0_p1: s0-p1@219 {
505 tsens_s0_p2: s0-p2@219 {
510 tsens_s1_p1: s1-p1@21a {
515 tsens_s1_p2: s1-p2@21b {
520 tsens_s2_p1: s2-p1@21c {
525 tsens_s2_p2: s2-p2@21c {
530 tsens_s3_p1: s3-p1@21d {
535 tsens_s3_p2: s3-p2@21e {
545 tsens_s4_p1: s4-p1@221 {
550 tsens_s4_p2: s4-p2@221 {
555 tsens_s5_p1: s5-p1@222 {
560 tsens_s5_p2: s5-p2@223 {
565 tsens_s6_p1: s6-p1@224 {
570 tsens_s6_p2: s6-p2@224 {
575 tsens_s7_p1: s7-p1@225 {
580 tsens_s7_p2: s7-p2@226 {
590 tsens_s8_p1: s8-p1@228 {
595 tsens_s8_p2: s8-p2@229 {
600 tsens_s9_p1: s9-p1@229 {
605 tsens_s9_p2: s9-p2@22a {
610 tsens_s10_p1: s10-p1@22b {
615 tsens_s10_p2: s10-p2@22c {
621 tsens: thermal-sensor@4a9000 {
622 compatible = "qcom,msm8976-tsens", "qcom,tsens-v1";
626 interrupt-names = "uplow";
627 nvmem-cells = <&tsens_mode>,
640 nvmem-cell-names = "mode",
654 #thermal-sensor-cells = <1>;
658 compatible = "qcom,msm8976-pinctrl";
661 #gpio-cells = <2>;
662 gpio-controller;
663 gpio-ranges = <&tlmm 0 0 145>;
664 interrupt-controller;
665 #interrupt-cells = <2>;
667 spi1_default: spi0-default-state {
668 spi-pins {
671 drive-strength = <12>;
672 bias-disable;
675 cs-pins {
678 drive-strength = <2>;
679 bias-disable;
683 spi1_sleep: spi0-sleep-state {
684 spi-pins {
687 drive-strength = <2>;
688 bias-pull-down;
691 cs-pins {
694 drive-strength = <2>;
695 bias-disable;
699 blsp1_i2c2_default: blsp1-i2c2-default-state {
702 drive-strength = <2>;
703 bias-disable;
706 blsp1_i2c2_sleep: blsp1-i2c2-sleep-state {
709 drive-strength = <2>;
710 bias-disable;
713 blsp1_i2c4_default: blsp1-i2c4-default-state {
716 drive-strength = <2>;
717 bias-disable;
720 blsp1_i2c4_sleep: blsp1-i2c4-sleep-state {
723 drive-strength = <2>;
724 bias-disable;
727 blsp2_uart2_active: blsp2-uart2-active-state {
730 drive-strength = <4>;
731 bias-disable;
734 blsp2_uart2_sleep: blsp2-uart2-sleep-state {
737 drive-strength = <2>;
738 bias-disable;
742 blsp2_i2c2_default: blsp2-i2c2-default-state {
745 drive-strength = <2>;
746 bias-disable;
749 blsp2_i2c2_sleep: blsp2-i2c2-sleep-state {
752 drive-strength = <2>;
753 bias-disable;
756 blsp2_i2c4_default: blsp2-i2c4-default-state {
759 drive-strength = <2>;
760 bias-disable;
763 blsp2_i2c4_sleep: blsp2-i2c4-sleep-state {
766 drive-strength = <2>;
767 bias-disable;
771 gcc: clock-controller@1800000 {
772 compatible = "qcom,gcc-msm8976";
774 #clock-cells = <1>;
775 #reset-cells = <1>;
776 #power-domain-cells = <1>;
778 assigned-clocks = <&gcc GPLL3>;
779 assigned-clock-rates = <1100000000>;
787 clock-names = "xo",
796 compatible = "qcom,tcsr-mutex";
798 #hwlock-cells = <1>;
802 compatible = "qcom,msm8976-tcsr", "syscon";
807 compatible = "qcom,spmi-pmic-arb";
813 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
815 interrupt-names = "periph_irq";
819 #address-cells = <2>;
820 #size-cells = <0>;
821 interrupt-controller;
822 #interrupt-cells = <4>;
826 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
828 reg-names = "hc", "core";
832 interrupt-names = "hc_irq", "pwr_irq";
837 clock-names = "iface", "core", "xo";
842 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
844 reg-names = "hc", "core";
848 interrupt-names = "hc_irq", "pwr_irq";
853 clock-names = "iface", "core", "xo";
857 blsp1_dma: dma-controller@7884000 {
858 compatible = "qcom,bam-v1.7.0";
862 clock-names = "bam_clk";
863 #dma-cells = <1>;
868 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
872 clock-names = "core", "iface";
874 dma-names = "tx", "rx";
879 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
883 clock-names = "core", "iface";
885 dma-names = "tx", "rx";
890 compatible = "qcom,spi-qup-v2.2.1";
894 clock-names = "core", "iface";
896 dma-names = "tx", "rx";
897 pinctrl-names = "default", "sleep";
898 pinctrl-0 = <&spi1_default>;
899 pinctrl-1 = <&spi1_sleep>;
900 #address-cells = <1>;
901 #size-cells = <0>;
906 compatible = "qcom,i2c-qup-v2.2.1";
910 clock-names = "core", "iface";
911 clock-frequency = <400000>;
913 dma-names = "tx", "rx";
914 pinctrl-names = "default", "sleep";
915 pinctrl-0 = <&blsp1_i2c2_default>;
916 pinctrl-1 = <&blsp1_i2c2_default>;
917 #address-cells = <1>;
918 #size-cells = <0>;
923 compatible = "qcom,i2c-qup-v2.2.1";
927 clock-names = "core", "iface";
928 clock-frequency = <400000>;
930 dma-names = "tx", "rx";
931 pinctrl-names = "default", "sleep";
932 pinctrl-0 = <&blsp1_i2c4_default>;
933 pinctrl-1 = <&blsp1_i2c4_sleep>;
934 #address-cells = <1>;
935 #size-cells = <0>;
940 compatible = "qcom,ci-hdrc";
946 clock-names = "iface", "core";
947 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
948 assigned-clock-rates = <80000000>;
950 reset-names = "core";
951 ahb-burst-config = <0>;
954 phy-names = "usb-phy";
957 #reset-cells = <1>;
961 compatible = "qcom,msm8976-sdhci", "qcom,sdhci-msm-v4";
963 reg-names = "hc", "core";
967 interrupt-names = "hc_irq", "pwr_irq";
972 clock-names = "iface", "core", "xo";
977 blsp2_dma: dma-controller@7ac4000 {
978 compatible = "qcom,bam-v1.7.0";
982 clock-names = "bam_clk";
983 #dma-cells = <1>;
988 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
992 clock-names = "core", "iface";
994 dma-names = "tx", "rx";
999 compatible = "qcom,i2c-qup-v2.2.1";
1003 clock-names = "core", "iface";
1004 clock-frequency = <400000>;
1006 dma-names = "tx", "rx";
1007 pinctrl-names = "default", "sleep";
1008 pinctrl-0 = <&blsp2_i2c2_default>;
1009 pinctrl-1 = <&blsp2_i2c2_sleep>;
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1016 compatible = "qcom,i2c-qup-v2.2.1";
1020 clock-names = "core", "iface";
1021 clock-frequency = <400000>;
1023 dma-names = "tx", "rx";
1024 pinctrl-names = "default", "sleep";
1025 pinctrl-0 = <&blsp2_i2c4_default>;
1026 pinctrl-1 = <&blsp2_i2c4_sleep>;
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1032 intc: interrupt-controller@b000000 {
1033 compatible = "qcom,msm-qgic2";
1035 interrupt-controller;
1036 #interrupt-cells = <3>;
1040 compatible = "qcom,msm8976-apcs-kpss-global",
1041 "qcom,msm8994-apcs-kpss-global", "syscon";
1043 #mbox-cells = <1>;
1047 compatible = "arm,armv7-timer-mem";
1049 #address-cells = <1>;
1050 #size-cells = <1>;
1052 clock-frequency = <19200000>;
1058 frame-number = <0>;
1064 frame-number = <1>;
1071 frame-number = <2>;
1078 frame-number = <3>;
1085 frame-number = <4>;
1092 frame-number = <5>;
1099 frame-number = <6>;
1105 compatible = "qcom,msm8976-imem", "syscon", "simple-mfd";
1107 #address-cells = <1>;
1108 #size-cells = <1>;
1112 pil-reloc@94c {
1113 compatible = "qcom,pil-reloc-info";
1119 thermal-zones {
1120 aoss0-thermal {
1121 polling-delay-passive = <250>;
1122 polling-delay = <1000>;
1124 thermal-sensors = <&tsens 0>;
1127 aoss0_alert0: trip-point0 {
1135 modem-thermal {
1136 polling-delay-passive = <250>;
1137 polling-delay = <1000>;
1139 thermal-sensors = <&tsens 1>;
1141 modem_alert0: trip-point0 {
1149 qdsp-thermal {
1150 polling-delay-passive = <250>;
1151 polling-delay = <1000>;
1153 thermal-sensors = <&tsens 2>;
1155 qdsp_alert0: trip-point0 {
1163 cam-isp-thermal {
1164 polling-delay-passive = <250>;
1165 polling-delay = <1000>;
1167 thermal-sensors = <&tsens 3>;
1169 cam_isp_alert0: trip-point0 {
1177 cpu4-thermal {
1178 polling-delay-passive = <250>;
1179 polling-delay = <1000>;
1180 thermal-sensors = <&tsens 4>;
1183 cpu4_alert0: trip-point0 {
1188 cpu4_alert1: trip-point1 {
1191 type = "passive";
1193 cpu4_crit: cpu-crit {
1201 cpu5-thermal {
1202 polling-delay-passive = <250>;
1203 polling-delay = <1000>;
1204 thermal-sensors = <&tsens 5>;
1207 cpu5_alert0: trip-point0 {
1212 cpu5_alert1: trip-point1 {
1215 type = "passive";
1217 cpu5_crit: cpu-crit {
1225 cpu6-thermal {
1226 polling-delay-passive = <250>;
1227 polling-delay = <1000>;
1228 thermal-sensors = <&tsens 6>;
1231 cpu6_alert0: trip-point0 {
1236 cpu6_alert1: trip-point1 {
1239 type = "passive";
1241 cpu6_crit: cpu-crit {
1249 cpu7-thermal {
1250 polling-delay-passive = <250>;
1251 polling-delay = <1000>;
1252 thermal-sensors = <&tsens 7>;
1255 cpu7_alert0: trip-point0 {
1260 cpu7_alert1: trip-point1 {
1263 type = "passive";
1265 cpu7_crit: cpu-crit {
1273 big-l2-thermal {
1274 polling-delay-passive = <250>;
1275 polling-delay = <1000>;
1276 thermal-sensors = <&tsens 8>;
1279 l2_alert0: trip-point0 {
1284 l2_alert1: trip-point1 {
1287 type = "passive";
1289 l2_crit: l2-crit {
1297 cpu0-thermal {
1298 polling-delay-passive = <250>;
1299 polling-delay = <1000>;
1300 thermal-sensors = <&tsens 9>;
1303 cpu0_alert0: trip-point0 {
1308 cpu0_alert1: trip-point1 {
1311 type = "passive";
1313 cpu0_crit: cpu-crit {
1321 gpu-thermal {
1322 polling-delay-passive = <250>;
1323 polling-delay = <1000>;
1324 thermal-sensors = <&tsens 10>;
1327 gpu_alert0: trip-point0 {
1332 gpu_alert1: trip-point1 {
1335 type = "passive";
1337 gpu_crit: gpu-crit {
1347 compatible = "arm,armv8-timer";
1352 clock-frequency = <19200000>;