Lines Matching refs:gcc
7 #include <dt-bindings/clock/qcom,gcc-msm8916.h>
12 #include <dt-bindings/reset/qcom,gcc-msm8916.h>
236 clocks = <&gcc GCC_CRYPTO_CLK>,
237 <&gcc GCC_CRYPTO_AXI_CLK>,
238 <&gcc GCC_CRYPTO_AHB_CLK>;
427 clocks = <&gcc GCC_PRNG_AHB_CLK>;
1481 gcc: clock-controller@1800000 { label
1482 compatible = "qcom,gcc-msm8916";
1521 power-domains = <&gcc MDSS_GDSC>;
1523 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1524 <&gcc GCC_MDSS_AXI_CLK>,
1525 <&gcc GCC_MDSS_VSYNC_CLK>;
1547 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1548 <&gcc GCC_MDSS_AXI_CLK>,
1549 <&gcc GCC_MDSS_MDP_CLK>,
1550 <&gcc GCC_MDSS_VSYNC_CLK>;
1580 assigned-clocks = <&gcc BYTE0_CLK_SRC>,
1581 <&gcc PCLK0_CLK_SRC>;
1585 clocks = <&gcc GCC_MDSS_MDP_CLK>,
1586 <&gcc GCC_MDSS_AHB_CLK>,
1587 <&gcc GCC_MDSS_AXI_CLK>,
1588 <&gcc GCC_MDSS_BYTE0_CLK>,
1589 <&gcc GCC_MDSS_PCLK0_CLK>,
1590 <&gcc GCC_MDSS_ESC0_CLK>;
1633 clocks = <&gcc GCC_MDSS_AHB_CLK>,
1671 power-domains = <&gcc VFE_GDSC>;
1672 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1673 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
1674 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
1675 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
1676 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
1677 <&gcc GCC_CAMSS_CSI0_CLK>,
1678 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
1679 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
1680 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
1681 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
1682 <&gcc GCC_CAMSS_CSI1_CLK>,
1683 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
1684 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
1685 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
1686 <&gcc GCC_CAMSS_AHB_CLK>,
1687 <&gcc GCC_CAMSS_VFE0_CLK>,
1688 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
1689 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
1690 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
1732 clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
1733 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1734 <&gcc GCC_CAMSS_CCI_CLK>,
1735 <&gcc GCC_CAMSS_AHB_CLK>;
1738 assigned-clocks = <&gcc GCC_CAMSS_CCI_AHB_CLK>,
1739 <&gcc GCC_CAMSS_CCI_CLK>;
1767 <&gcc GCC_OXILI_GFX3D_CLK>,
1768 <&gcc GCC_OXILI_AHB_CLK>,
1769 <&gcc GCC_OXILI_GMEM_CLK>,
1770 <&gcc GCC_BIMC_GFX_CLK>,
1771 <&gcc GCC_BIMC_GPU_CLK>,
1772 <&gcc GFX3D_CLK_SRC>;
1773 power-domains = <&gcc OXILI_GDSC>;
1793 power-domains = <&gcc VENUS_GDSC>;
1794 clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>,
1795 <&gcc GCC_VENUS0_AHB_CLK>,
1796 <&gcc GCC_VENUS0_AXI_CLK>;
1818 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1819 <&gcc GCC_APSS_TCU_CLK>;
1851 clocks = <&gcc GCC_SMMU_CFG_CLK>,
1852 <&gcc GCC_GFX_TCU_CLK>;
1922 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1923 <&gcc GCC_MSS_Q6_BIMC_AXI_CLK>,
1924 <&gcc GCC_BOOT_ROM_AHB_CLK>,
2004 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2005 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2006 <&gcc GCC_ULTAUDIO_LPAIF_PRI_I2S_CLK>,
2007 <&gcc GCC_ULTAUDIO_LPAIF_SEC_I2S_CLK>,
2008 <&gcc GCC_ULTAUDIO_LPAIF_AUX_I2S_CLK>,
2009 <&gcc GCC_ULTAUDIO_PCNOC_MPORT_CLK>,
2010 <&gcc GCC_ULTAUDIO_PCNOC_SWAY_CLK>;
2033 clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>,
2034 <&gcc GCC_CODEC_DIGCODEC_CLK>;
2048 clocks = <&gcc GCC_SDCC1_AHB_CLK>,
2049 <&gcc GCC_SDCC1_APPS_CLK>,
2069 clocks = <&gcc GCC_SDCC2_AHB_CLK>,
2070 <&gcc GCC_SDCC2_APPS_CLK>,
2084 clocks = <&gcc GCC_BLSP1_AHB_CLK>;
2094 clocks = <&gcc GCC_BLSP1_UART1_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2108 clocks = <&gcc GCC_BLSP1_UART2_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
2122 clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>,
2123 <&gcc GCC_BLSP1_AHB_CLK>;
2139 clocks = <&gcc GCC_BLSP1_QUP1_SPI_APPS_CLK>,
2140 <&gcc GCC_BLSP1_AHB_CLK>;
2156 clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>,
2157 <&gcc GCC_BLSP1_AHB_CLK>;
2173 clocks = <&gcc GCC_BLSP1_QUP2_SPI_APPS_CLK>,
2174 <&gcc GCC_BLSP1_AHB_CLK>;
2190 clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>,
2191 <&gcc GCC_BLSP1_AHB_CLK>;
2207 clocks = <&gcc GCC_BLSP1_QUP3_SPI_APPS_CLK>,
2208 <&gcc GCC_BLSP1_AHB_CLK>;
2224 clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>,
2225 <&gcc GCC_BLSP1_AHB_CLK>;
2241 clocks = <&gcc GCC_BLSP1_QUP4_SPI_APPS_CLK>,
2242 <&gcc GCC_BLSP1_AHB_CLK>;
2258 clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>,
2259 <&gcc GCC_BLSP1_AHB_CLK>;
2275 clocks = <&gcc GCC_BLSP1_QUP5_SPI_APPS_CLK>,
2276 <&gcc GCC_BLSP1_AHB_CLK>;
2292 clocks = <&gcc GCC_BLSP1_QUP6_I2C_APPS_CLK>,
2293 <&gcc GCC_BLSP1_AHB_CLK>;
2309 clocks = <&gcc GCC_BLSP1_QUP6_SPI_APPS_CLK>,
2310 <&gcc GCC_BLSP1_AHB_CLK>;
2328 clocks = <&gcc GCC_USB_HS_AHB_CLK>,
2329 <&gcc GCC_USB_HS_SYSTEM_CLK>;
2331 assigned-clocks = <&gcc GCC_USB_HS_SYSTEM_CLK>;
2333 resets = <&gcc GCC_USB_HS_BCR>;
2351 clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
2353 resets = <&gcc GCC_USB2A_PHY_BCR>, <&usb 0>;
2441 clocks = <&a53pll>, <&gcc GPLL0_VOTE>;