Lines Matching +full:thermal +full:- +full:sensors
1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
5 * Copyright (c) 2020-2021 The Linux Foundation. All rights reserved.
9 #include <dt-bindings/clock/qcom,apss-ipq.h>
10 #include <dt-bindings/clock/qcom,ipq9574-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/reset/qcom,ipq9574-gcc.h>
13 #include <dt-bindings/thermal/thermal.h>
16 interrupt-parent = <&intc>;
17 #address-cells = <2>;
18 #size-cells = <2>;
21 sleep_clk: sleep-clk {
22 compatible = "fixed-clock";
23 #clock-cells = <0>;
26 xo_board_clk: xo-board-clk {
27 compatible = "fixed-clock";
28 #clock-cells = <0>;
33 #address-cells = <1>;
34 #size-cells = <0>;
38 compatible = "arm,cortex-a73";
40 enable-method = "psci";
41 next-level-cache = <&L2_0>;
43 clock-names = "cpu";
44 operating-points-v2 = <&cpu_opp_table>;
45 cpu-supply = <&ipq9574_s1>;
46 #cooling-cells = <2>;
51 compatible = "arm,cortex-a73";
53 enable-method = "psci";
54 next-level-cache = <&L2_0>;
56 clock-names = "cpu";
57 operating-points-v2 = <&cpu_opp_table>;
58 cpu-supply = <&ipq9574_s1>;
59 #cooling-cells = <2>;
64 compatible = "arm,cortex-a73";
66 enable-method = "psci";
67 next-level-cache = <&L2_0>;
69 clock-names = "cpu";
70 operating-points-v2 = <&cpu_opp_table>;
71 cpu-supply = <&ipq9574_s1>;
72 #cooling-cells = <2>;
77 compatible = "arm,cortex-a73";
79 enable-method = "psci";
80 next-level-cache = <&L2_0>;
82 clock-names = "cpu";
83 operating-points-v2 = <&cpu_opp_table>;
84 cpu-supply = <&ipq9574_s1>;
85 #cooling-cells = <2>;
88 L2_0: l2-cache {
90 cache-level = <2>;
91 cache-unified;
97 compatible = "qcom,scm-ipq9574", "qcom,scm";
98 qcom,dload-mode = <&tcsr 0x6100>;
108 cpu_opp_table: opp-table-cpu {
109 compatible = "operating-points-v2";
110 opp-shared;
112 opp-936000000 {
113 opp-hz = /bits/ 64 <936000000>;
114 opp-microvolt = <725000>;
115 clock-latency-ns = <200000>;
118 opp-1104000000 {
119 opp-hz = /bits/ 64 <1104000000>;
120 opp-microvolt = <787500>;
121 clock-latency-ns = <200000>;
124 opp-1416000000 {
125 opp-hz = /bits/ 64 <1416000000>;
126 opp-microvolt = <862500>;
127 clock-latency-ns = <200000>;
130 opp-1488000000 {
131 opp-hz = /bits/ 64 <1488000000>;
132 opp-microvolt = <925000>;
133 clock-latency-ns = <200000>;
136 opp-1800000000 {
137 opp-hz = /bits/ 64 <1800000000>;
138 opp-microvolt = <987500>;
139 clock-latency-ns = <200000>;
142 opp-2208000000 {
143 opp-hz = /bits/ 64 <2208000000>;
144 opp-microvolt = <1062500>;
145 clock-latency-ns = <200000>;
150 compatible = "arm,cortex-a73-pmu";
155 compatible = "arm,psci-1.0";
160 compatible = "qcom,ipq9574-rpm-proc", "qcom,rpm-proc";
162 glink-edge {
163 compatible = "qcom,glink-rpm";
165 qcom,rpm-msg-ram = <&rpm_msg_ram>;
168 rpm_requests: rpm-requests {
169 compatible = "qcom,rpm-ipq9574";
170 qcom,glink-channels = "rpm_requests";
175 reserved-memory {
176 #address-cells = <2>;
177 #size-cells = <2>;
182 no-map;
187 no-map;
192 no-map;
199 no-map;
204 compatible = "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <1>;
210 compatible = "qcom,rpm-msg-ram";
215 compatible = "qcom,prng-ee";
218 clock-names = "core";
222 compatible = "qcom,ipq9574-qfprom", "qcom,qfprom";
224 #address-cells = <1>;
225 #size-cells = <1>;
228 cryptobam: dma-controller@704000 {
229 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
232 #dma-cells = <1>;
234 qcom,controlled-remotely;
238 compatible = "qcom,ipq9574-qce", "qcom,ipq4019-qce", "qcom,qce";
243 clock-names = "iface", "bus", "core";
245 dma-names = "rx", "tx";
248 tsens: thermal-sensor@4a9000 {
249 compatible = "qcom,ipq9574-tsens", "qcom,ipq8074-tsens";
253 interrupt-names = "combined";
254 #qcom,sensors = <16>;
255 #thermal-sensor-cells = <1>;
259 compatible = "qcom,ipq9574-tlmm";
262 gpio-controller;
263 #gpio-cells = <2>;
264 gpio-ranges = <&tlmm 0 0 65>;
265 interrupt-controller;
266 #interrupt-cells = <2>;
268 uart2_pins: uart2-state {
271 drive-strength = <8>;
272 bias-disable;
276 gcc: clock-controller@1800000 {
277 compatible = "qcom,ipq9574-gcc";
287 #clock-cells = <1>;
288 #reset-cells = <1>;
289 #power-domain-cells = <1>;
293 compatible = "qcom,tcsr-mutex";
295 #hwlock-cells = <1>;
299 compatible = "qcom,tcsr-ipq9574", "syscon";
304 compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
306 reg-names = "hc", "cqhci";
310 interrupt-names = "hc_irq", "pwr_irq";
315 clock-names = "iface", "core", "xo";
316 non-removable;
320 blsp_dma: dma-controller@7884000 {
321 compatible = "qcom,bam-v1.7.0";
325 clock-names = "bam_clk";
326 #dma-cells = <1>;
331 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
336 clock-names = "core", "iface";
341 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
346 clock-names = "core", "iface";
351 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
356 clock-names = "core", "iface";
361 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
366 clock-names = "core", "iface";
371 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
376 clock-names = "core", "iface";
381 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
386 clock-names = "core", "iface";
391 compatible = "qcom,spi-qup-v2.2.1";
393 #address-cells = <1>;
394 #size-cells = <0>;
398 clock-names = "core", "iface";
400 dma-names = "tx", "rx";
405 compatible = "qcom,i2c-qup-v2.2.1";
407 #address-cells = <1>;
408 #size-cells = <0>;
412 clock-names = "core", "iface";
413 assigned-clocks = <&gcc GCC_BLSP1_QUP2_I2C_APPS_CLK>;
414 assigned-clock-rates = <50000000>;
416 dma-names = "tx", "rx";
421 compatible = "qcom,spi-qup-v2.2.1";
423 #address-cells = <1>;
424 #size-cells = <0>;
428 clock-names = "core", "iface";
430 dma-names = "tx", "rx";
435 compatible = "qcom,i2c-qup-v2.2.1";
437 #address-cells = <1>;
438 #size-cells = <0>;
442 clock-names = "core", "iface";
443 assigned-clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>;
444 assigned-clock-rates = <50000000>;
446 dma-names = "tx", "rx";
451 compatible = "qcom,spi-qup-v2.2.1";
453 #address-cells = <1>;
454 #size-cells = <0>;
458 clock-names = "core", "iface";
460 dma-names = "tx", "rx";
465 compatible = "qcom,i2c-qup-v2.2.1";
467 #address-cells = <1>;
468 #size-cells = <0>;
472 clock-names = "core", "iface";
473 assigned-clocks = <&gcc GCC_BLSP1_QUP4_I2C_APPS_CLK>;
474 assigned-clock-rates = <50000000>;
476 dma-names = "tx", "rx";
481 compatible = "qcom,spi-qup-v2.2.1";
483 #address-cells = <1>;
484 #size-cells = <0>;
486 spi-max-frequency = <50000000>;
489 clock-names = "core", "iface";
491 dma-names = "tx", "rx";
496 compatible = "qcom,i2c-qup-v2.2.1";
498 #address-cells = <1>;
499 #size-cells = <0>;
503 clock-names = "core", "iface";
504 assigned-clocks = <&gcc GCC_BLSP1_QUP5_I2C_APPS_CLK>;
505 assigned-clock-rates = <50000000>;
507 dma-names = "tx", "rx";
512 compatible = "qcom,spi-qup-v2.2.1";
514 #address-cells = <1>;
515 #size-cells = <0>;
519 clock-names = "core", "iface";
521 dma-names = "tx", "rx";
526 compatible = "qcom,ipq9574-qusb2-phy";
528 #phy-cells = <0>;
532 clock-names = "cfg_ahb",
540 compatible = "qcom,ipq9574-qmp-usb3-phy";
542 #phy-cells = <0>;
548 clock-names = "aux",
555 reset-names = "phy",
558 #clock-cells = <0>;
559 clock-output-names = "usb0_pipe_clk";
565 compatible = "qcom,ipq9574-dwc3", "qcom,dwc3";
567 #address-cells = <1>;
568 #size-cells = <1>;
577 clock-names = "cfg_noc",
583 assigned-clocks = <&gcc GCC_USB0_MASTER_CLK>,
585 assigned-clock-rates = <200000000>,
588 interrupts-extended = <&intc GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
589 interrupt-names = "pwr_event";
598 clock-names = "ref";
601 phy-names = "usb2-phy", "usb3-phy";
602 tx-fifo-resize;
603 snps,is-utmi-l1-suspend;
604 snps,hird-threshold = /bits/ 8 <0x0>;
610 intc: interrupt-controller@b000000 {
611 compatible = "qcom,msm-qgic2";
616 #address-cells = <1>;
617 #size-cells = <1>;
618 interrupt-controller;
619 #interrupt-cells = <3>;
624 compatible = "arm,gic-v2m-frame";
626 msi-controller;
630 compatible = "arm,gic-v2m-frame";
632 msi-controller;
636 compatible = "arm,gic-v2m-frame";
638 msi-controller;
643 compatible = "qcom,apss-wdt-ipq9574", "qcom,kpss-wdt";
647 timeout-sec = <30>;
651 compatible = "qcom,ipq9574-apcs-apps-global",
652 "qcom,ipq6018-apcs-apps-global";
654 #clock-cells = <1>;
656 clock-names = "pll", "xo";
657 #mbox-cells = <1>;
661 compatible = "qcom,ipq9574-a73pll";
663 #clock-cells = <0>;
665 clock-names = "xo";
669 compatible = "arm,armv7-timer-mem";
671 #address-cells = <1>;
672 #size-cells = <1>;
678 frame-number = <0>;
685 frame-number = <1>;
692 frame-number = <2>;
699 frame-number = <3>;
706 frame-number = <4>;
713 frame-number = <5>;
720 frame-number = <6>;
727 thermal-zones {
728 nss-top-thermal {
729 polling-delay-passive = <0>;
730 polling-delay = <0>;
731 thermal-sensors = <&tsens 3>;
734 nss-top-critical {
742 ubi-0-thermal {
743 polling-delay-passive = <0>;
744 polling-delay = <0>;
745 thermal-sensors = <&tsens 4>;
748 ubi_0-critical {
756 ubi-1-thermal {
757 polling-delay-passive = <0>;
758 polling-delay = <0>;
759 thermal-sensors = <&tsens 5>;
762 ubi_1-critical {
770 ubi-2-thermal {
771 polling-delay-passive = <0>;
772 polling-delay = <0>;
773 thermal-sensors = <&tsens 6>;
776 ubi_2-critical {
784 ubi-3-thermal {
785 polling-delay-passive = <0>;
786 polling-delay = <0>;
787 thermal-sensors = <&tsens 7>;
790 ubi_3-critical {
798 cpuss0-thermal {
799 polling-delay-passive = <0>;
800 polling-delay = <0>;
801 thermal-sensors = <&tsens 8>;
804 cpu-critical {
812 cpuss1-thermal {
813 polling-delay-passive = <0>;
814 polling-delay = <0>;
815 thermal-sensors = <&tsens 9>;
818 cpu-critical {
826 cpu0-thermal {
827 polling-delay-passive = <0>;
828 polling-delay = <0>;
829 thermal-sensors = <&tsens 10>;
832 cpu0_crit: cpu-critical {
838 cpu0_alert: cpu-passive {
845 cooling-maps {
848 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
856 cpu1-thermal {
857 polling-delay-passive = <0>;
858 polling-delay = <0>;
859 thermal-sensors = <&tsens 11>;
862 cpu1_crit: cpu-critical {
868 cpu1_alert: cpu-passive {
875 cooling-maps {
878 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
886 cpu2-thermal {
887 polling-delay-passive = <0>;
888 polling-delay = <0>;
889 thermal-sensors = <&tsens 12>;
892 cpu2_crit: cpu-critical {
898 cpu2_alert: cpu-passive {
905 cooling-maps {
908 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
916 cpu3-thermal {
917 polling-delay-passive = <0>;
918 polling-delay = <0>;
919 thermal-sensors = <&tsens 13>;
922 cpu3_crit: cpu-critical {
928 cpu3_alert: cpu-passive {
935 cooling-maps {
938 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
946 wcss-phyb-thermal {
947 polling-delay-passive = <0>;
948 polling-delay = <0>;
949 thermal-sensors = <&tsens 14>;
952 wcss_phyb-critical {
960 top-glue-thermal {
961 polling-delay-passive = <0>;
962 polling-delay = <0>;
963 thermal-sensors = <&tsens 15>;
966 top_glue-critical {
976 compatible = "arm,armv8-timer";