Lines Matching +full:0 +full:x34000000
19 bus@0 {
24 ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;
28 reg = <0x0 0x00100000 0x0 0xf000>,
29 <0x0 0x0010f000 0x0 0x1000>;
35 reg = <0x0 0x02080000 0x0 0x00121000>;
36 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
58 reg = <0x0 0x02200000 0x0 0x10000>,
59 <0x0 0x02210000 0x0 0x10000>;
112 gpio-ranges = <&pinmux 0 0 164>;
117 reg = <0x0 0x2430000 0x0 0x19100>;
123 reg = <0x0 0x2600000 0x0 0x210000>;
160 dma-channel-mask = <0xfffffffe>;
175 ranges = <0x0 0x02900000 0x0 0x02900000 0x0 0x200000>;
179 reg = <0x0 0x02900800 0x0 0x800>;
189 ranges = <0x0 0x02900800 0x0 0x02900800 0x0 0x11800>;
194 reg = <0x0 0x2901000 0x0 0x100>;
208 reg = <0x0 0x2901100 0x0 0x100>;
222 reg = <0x0 0x2901200 0x0 0x100>;
236 reg = <0x0 0x2901300 0x0 0x100>;
250 reg = <0x0 0x2901400 0x0 0x100>;
264 reg = <0x0 0x2901500 0x0 0x100>;
278 reg = <0x0 0x2902000 0x0 0x200>;
286 reg = <0x0 0x2902200 0x0 0x200>;
294 reg = <0x0 0x2902400 0x0 0x200>;
302 reg = <0x0 0x2902600 0x0 0x200>;
310 reg = <0x0 0x2903000 0x0 0x100>;
318 reg = <0x0 0x2903100 0x0 0x100>;
326 reg = <0x0 0x2903200 0x0 0x100>;
334 reg = <0x0 0x2903300 0x0 0x100>;
342 reg = <0x0 0x2903800 0x0 0x100>;
350 reg = <0x0 0x2903900 0x0 0x100>;
358 reg = <0x0 0x2903a00 0x0 0x100>;
366 reg = <0x0 0x2903b00 0x0 0x100>;
375 reg = <0x0 0x2904000 0x0 0x100>;
388 reg = <0x0 0x2904100 0x0 0x100>;
401 reg = <0x0 0x2904200 0x0 0x100>;
414 reg = <0x0 0x2904300 0x0 0x100>;
427 reg = <0x0 0x2905000 0x0 0x100>;
440 reg = <0x0 0x2905100 0x0 0x100>;
453 reg = <0x0 0x2908000 0x0 0x100>;
464 reg = <0x0 0x2908100 0x0 0x100>;
470 reg = <0x0 0x2908200 0x0 0x200>;
477 reg = <0x0 0x290a000 0x0 0x200>;
485 reg = <0x0 0x290a200 0x0 0x200>;
493 reg = <0x0 0x290bb00 0x0 0x800>;
501 reg = <0x0 0x0290f000 0x0 0x1000>;
552 reg = <0x0 0x2910000 0x0 0x2000>;
561 reg = <0x0 0x02930000 0x0 0x20000>;
563 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
606 reg = <0x0 0x02a41000 0x0 0x1000>,
607 <0x0 0x02a42000 0x0 0x2000>;
619 reg = <0x0 0x02c00000 0x0 0x10000>, /* MC-SID */
620 <0x0 0x02c10000 0x0 0x10000>, /* MC Broadcast*/
621 <0x0 0x02c20000 0x0 0x10000>, /* MC0 */
622 <0x0 0x02c30000 0x0 0x10000>, /* MC1 */
623 <0x0 0x02c40000 0x0 0x10000>, /* MC2 */
624 <0x0 0x02c50000 0x0 0x10000>, /* MC3 */
625 <0x0 0x02b80000 0x0 0x10000>, /* MC4 */
626 <0x0 0x02b90000 0x0 0x10000>, /* MC5 */
627 <0x0 0x02ba0000 0x0 0x10000>, /* MC6 */
628 <0x0 0x02bb0000 0x0 0x10000>, /* MC7 */
629 <0x0 0x01700000 0x0 0x10000>, /* MC8 */
630 <0x0 0x01710000 0x0 0x10000>, /* MC9 */
631 <0x0 0x01720000 0x0 0x10000>, /* MC10 */
632 <0x0 0x01730000 0x0 0x10000>, /* MC11 */
633 <0x0 0x01740000 0x0 0x10000>, /* MC12 */
634 <0x0 0x01750000 0x0 0x10000>, /* MC13 */
635 <0x0 0x01760000 0x0 0x10000>, /* MC14 */
636 <0x0 0x01770000 0x0 0x10000>; /* MC15 */
646 ranges = <0x0 0x01700000 0x0 0x01700000 0x0 0x100000>,
647 <0x0 0x02b80000 0x0 0x02b80000 0x0 0x040000>,
648 <0x0 0x02c00000 0x0 0x02c00000 0x0 0x100000>;
663 * Limit the DMA range for memory clients to [38:0].
665 dma-ranges = <0x0 0x0 0x0 0x0 0x80 0x0>;
669 reg = <0x0 0x02c60000 0x0 0x90000>,
670 <0x0 0x01780000 0x0 0x80000>;
676 #interconnect-cells = <0>;
684 reg = <0x0 0x03100000 0x0 0x10000>;
693 reg = <0x0 0x03140000 0x0 0x10000>;
702 reg = <0x0 0x3160000 0x0 0x100>;
706 #size-cells = <0>;
721 reg = <0x0 0x3180000 0x0 0x100>;
724 #size-cells = <0>;
740 reg = <0x0 0x3190000 0x0 0x100>;
743 #size-cells = <0>;
759 reg = <0x0 0x31b0000 0x0 0x100>;
762 #size-cells = <0>;
778 reg = <0x0 0x31c0000 0x0 0x100>;
781 #size-cells = <0>;
797 reg = <0x0 0x31d0000 0x0 0x10000>;
804 reg = <0x0 0x31e0000 0x0 0x100>;
807 #size-cells = <0>;
823 reg = <0x0 0x03210000 0x0 0x1000>;
826 #size-cells = <0>;
842 reg = <0x0 0x03230000 0x0 0x1000>;
845 #size-cells = <0>;
861 reg = <0x0 0x3270000 0x0 0x1000>;
864 #size-cells = <0>;
874 reg = <0x0 0x3280000 0x0 0x10000>;
884 reg = <0x0 0x3290000 0x0 0x10000>;
894 reg = <0x0 0x32a0000 0x0 0x10000>;
904 reg = <0x0 0x32c0000 0x0 0x10000>;
914 reg = <0x0 0x32d0000 0x0 0x10000>;
924 reg = <0x0 0x32e0000 0x0 0x10000>;
934 reg = <0x0 0x32f0000 0x0 0x10000>;
944 reg = <0x0 0x3300000 0x0 0x1000>;
947 #size-cells = <0>;
957 reg = <0x0 0x03400000 0x0 0x20000>;
973 pinctrl-0 = <&sdmmc1_3v3>;
975 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x07>;
976 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x07>;
977 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x06>;
978 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x07>;
979 nvidia,pad-autocal-pull-up-offset-sdr104 = <0x00>;
980 nvidia,pad-autocal-pull-down-offset-sdr104 = <0x00>;
982 nvidia,default-trim = <0x8>;
992 reg = <0x0 0x03460000 0x0 0x20000>;
1006 nvidia,pad-autocal-pull-up-offset-hs400 = <0x00>;
1007 nvidia,pad-autocal-pull-down-offset-hs400 = <0x00>;
1008 nvidia,pad-autocal-pull-up-offset-1v8-timeout = <0x0a>;
1009 nvidia,pad-autocal-pull-down-offset-1v8-timeout = <0x0a>;
1010 nvidia,pad-autocal-pull-up-offset-3v3-timeout = <0x0a>;
1011 nvidia,pad-autocal-pull-down-offset-3v3-timeout = <0x0a>;
1012 nvidia,default-tap = <0x8>;
1013 nvidia,default-trim = <0x14>;
1021 reg = <0x0 0x3510000 0x0 0x10000>;
1039 reg = <0x0 0x03520000 0x0 0x20000>,
1040 <0x0 0x03540000 0x0 0x10000>;
1055 usb2-0 {
1058 #phy-cells = <0>;
1064 #phy-cells = <0>;
1070 #phy-cells = <0>;
1076 #phy-cells = <0>;
1083 usb3-0 {
1086 #phy-cells = <0>;
1092 #phy-cells = <0>;
1098 #phy-cells = <0>;
1104 #phy-cells = <0>;
1111 usb2-0 {
1127 usb3-0 {
1147 reg = <0x0 0x03550000 0x0 0x8000>,
1148 <0x0 0x03558000 0x0 0x8000>;
1170 reg = <0x0 0x03610000 0x0 0x40000>,
1171 <0x0 0x03600000 0x0 0x10000>,
1172 <0x0 0x03650000 0x0 0x10000>;
1207 reg = <0x0 0x03810000 0x0 0x10000>;
1214 reg = <0x0 0x3aa0000 0x0 0x10000>;
1222 reg = <0x0 0x03c00000 0x0 0xa0000>;
1240 reg = <0x0 0x03e00000 0x0 0x10000>;
1243 #phy-cells = <0>;
1248 reg = <0x0 0x03e10000 0x0 0x10000>;
1251 #phy-cells = <0>;
1256 reg = <0x0 0x03e20000 0x0 0x10000>;
1259 #phy-cells = <0>;
1264 reg = <0x0 0x03e30000 0x0 0x10000>;
1267 #phy-cells = <0>;
1272 reg = <0x0 0x03e40000 0x0 0x10000>;
1275 #phy-cells = <0>;
1280 reg = <0x0 0x03e50000 0x0 0x10000>;
1283 #phy-cells = <0>;
1288 reg = <0x0 0x03e60000 0x0 0x10000>;
1291 #phy-cells = <0>;
1296 reg = <0x0 0x03e70000 0x0 0x10000>;
1299 #phy-cells = <0>;
1304 reg = <0x0 0x03e90000 0x0 0x10000>;
1307 #phy-cells = <0>;
1312 reg = <0x0 0x03ea0000 0x0 0x10000>;
1315 #phy-cells = <0>;
1320 reg = <0x0 0x03eb0000 0x0 0x10000>;
1323 #phy-cells = <0>;
1328 reg = <0x0 0x03ec0000 0x0 0x10000>;
1331 #phy-cells = <0>;
1336 reg = <0x0 0x03ed0000 0x0 0x10000>;
1339 #phy-cells = <0>;
1344 reg = <0x0 0x03ee0000 0x0 0x10000>;
1347 #phy-cells = <0>;
1352 reg = <0x0 0x03ef0000 0x0 0x10000>;
1355 #phy-cells = <0>;
1360 reg = <0x0 0x03f00000 0x0 0x10000>;
1363 #phy-cells = <0>;
1368 reg = <0x0 0x03f20000 0x0 0x10000>;
1371 #phy-cells = <0>;
1376 reg = <0x0 0x03f30000 0x0 0x10000>;
1379 #phy-cells = <0>;
1384 reg = <0x0 0x03f40000 0x0 0x10000>;
1387 #phy-cells = <0>;
1392 reg = <0x0 0x03f50000 0x0 0x10000>;
1395 #phy-cells = <0>;
1400 reg = <0x0 0x03f60000 0x0 0x10000>;
1403 #phy-cells = <0>;
1408 reg = <0x0 0x03f70000 0x0 0x10000>;
1411 #phy-cells = <0>;
1416 reg = <0x0 0x03f80000 0x0 0x10000>;
1419 #phy-cells = <0>;
1424 reg = <0x0 0x03f90000 0x0 0x10000>;
1427 #phy-cells = <0>;
1432 reg = <0x0 0x06800000 0x0 0x10000>,
1433 <0x0 0x06810000 0x0 0x10000>,
1434 <0x0 0x068a0000 0x0 0x10000>;
1466 reg = <0x0 0x06900000 0x0 0x10000>,
1467 <0x0 0x06910000 0x0 0x10000>,
1468 <0x0 0x069a0000 0x0 0x10000>;
1500 reg = <0x0 0x06a00000 0x0 0x10000>,
1501 <0x0 0x06a10000 0x0 0x10000>,
1502 <0x0 0x06aa0000 0x0 0x10000>;
1534 reg = <0x0 0x06b00000 0x0 0x10000>,
1535 <0x0 0x06b10000 0x0 0x10000>,
1536 <0x0 0x06ba0000 0x0 0x10000>;
1568 reg = <0x0 0x8000000 0x0 0x1000000>,
1569 <0x0 0x7000000 0x0 0x1000000>;
1700 stream-match-mask = <0x7f80>;
1710 reg = <0x0 0xb600000 0x0 0x40000>;
1717 reg = <0x0 0xbe00000 0x0 0x40000>;
1724 reg = <0x0 0x0c150000 0x0 0x90000>;
1730 * Shared interrupt 0 is routed only to AON/SPE, so
1739 reg = <0x0 0xc1e0000 0x0 0x10000>;
1748 reg = <0x0 0xc240000 0x0 0x100>;
1751 #size-cells = <0>;
1767 reg = <0x0 0xc250000 0x0 0x100>;
1770 #size-cells = <0>;
1780 dmas = <&gpcdma 0>, <&gpcdma 0>;
1786 reg = <0x0 0x0c260000 0x0 0x1000>;
1789 #size-cells = <0>;
1805 reg = <0x0 0x0c2a0000 0x0 0x10000>;
1816 reg = <0x0 0x0c2f0000 0x0 0x1000>,
1817 <0x0 0x0c2f1000 0x0 0x1000>;
1826 gpio-ranges = <&pinmux_aon 0 0 32>;
1831 reg = <0x0 0xc300000 0x0 0x4000>;
1836 reg = <0x0 0xc340000 0x0 0x10000>;
1846 reg = <0x0 0x0c360000 0x0 0x10000>,
1847 <0x0 0x0c370000 0x0 0x10000>,
1848 <0x0 0x0c380000 0x0 0x10000>,
1849 <0x0 0x0c390000 0x0 0x10000>,
1850 <0x0 0x0c3a0000 0x0 0x10000>;
1879 reg = <0x0 0xc600000 0x0 0x40000>;
1886 reg = <0x0 0xd600000 0x0 0x40000>;
1893 reg = <0x0 0xde00000 0x0 0x40000>;
1900 reg = <0x0 0x0e000000 0x0 0x5ffff>;
1907 reg = <0x0 0x0f400000 0x0 0x010000>, /* GICD */
1908 <0x0 0x0f440000 0x0 0x200000>; /* GICR */
1919 reg = <0x0 0x10000000 0x0 0x1000000>;
2049 stream-match-mask = <0x7f80>;
2059 reg = <0x0 0x12000000 0x0 0x1000000>,
2060 <0x0 0x11000000 0x0 0x1000000>;
2191 stream-match-mask = <0x7f80>;
2201 reg = <0x0 0x13a00000 0x0 0x400000>;
2208 reg = <0x0 0x13e00000 0x0 0x10000>,
2209 <0x0 0x13e10000 0x0 0x10000>,
2210 <0x0 0x13e40000 0x0 0x10000>;
2228 ranges = <0x0 0x14800000 0x0 0x14800000 0x0 0x02000000>;
2236 iommu-map = <0 &smmu_niso0 TEGRA234_SID_HOST1X_CTX0 1>,
2255 reg = <0x0 0x15340000 0x0 0x00040000>;
2272 reg = <0x0 0x15480000 0x0 0x00040000>;
2292 nvidia,bl-manifest-offset = <0>;
2293 nvidia,bl-data-offset = <0>;
2294 nvidia,bl-code-offset = <0>;
2295 nvidia,os-manifest-offset = <0>;
2296 nvidia,os-data-offset = <0>;
2297 nvidia,os-code-offset = <0>;
2310 reg = <0x00 0x140a0000 0x0 0x00020000>, /* appl registers (128K) */
2311 <0x00 0x2a000000 0x0 0x00040000>, /* configuration space (256K) */
2312 <0x00 0x2a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2313 <0x00 0x2a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2314 <0x35 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2336 interrupt-map-mask = <0 0 0 0>;
2337 interrupt-map = <0 0 0 0 &gic GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
2345 bus-range = <0x0 0xff>;
2347 …ranges = <0x43000000 0x32 0x40000000 0x32 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2348 …<0x02000000 0x0 0x40000000 0x35 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2349 <0x01000000 0x0 0x2a100000 0x00 0x2a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2354 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE8 0x1000>;
2355 iommu-map-mask = <0x0>;
2364 reg = <0x00 0x140c0000 0x0 0x00020000>, /* appl registers (128K) */
2365 <0x00 0x2c000000 0x0 0x00040000>, /* configuration space (256K) */
2366 <0x00 0x2c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2367 <0x00 0x2c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2368 <0x38 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2390 interrupt-map-mask = <0 0 0 0>;
2391 interrupt-map = <0 0 0 0 &gic GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
2399 bus-range = <0x0 0xff>;
2401 …ranges = <0x43000000 0x35 0x40000000 0x35 0x40000000 0x2 0xc0000000>, /* prefetchable memory (1126…
2402 …<0x02000000 0x0 0x40000000 0x38 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2403 <0x01000000 0x0 0x2c100000 0x00 0x2c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2408 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE9 0x1000>;
2409 iommu-map-mask = <0x0>;
2418 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2419 <0x00 0x2e000000 0x0 0x00040000>, /* configuration space (256K) */
2420 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2421 <0x00 0x2e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2422 <0x3b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2444 interrupt-map-mask = <0 0 0 0>;
2445 interrupt-map = <0 0 0 0 &gic GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>;
2453 bus-range = <0x0 0xff>;
2455 …ranges = <0x43000000 0x38 0x40000000 0x38 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2456 …<0x02000000 0x0 0x40000000 0x3b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2457 <0x01000000 0x0 0x2e100000 0x00 0x2e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2462 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2463 iommu-map-mask = <0x0>;
2472 reg = <0x00 0x140e0000 0x0 0x00020000>, /* appl registers (128K) */
2473 <0x00 0x2e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2474 <0x00 0x2e080000 0x0 0x00040000>, /* DBI space (256K) */
2475 <0x38 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2500 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE10 0x1000>;
2501 iommu-map-mask = <0x0>;
2510 reg = <0x00 0x14100000 0x0 0x00020000>, /* appl registers (128K) */
2511 <0x00 0x30000000 0x0 0x00040000>, /* configuration space (256K) */
2512 <0x00 0x30040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2513 <0x00 0x30080000 0x0 0x00040000>, /* DBI reg space (256K) */
2514 <0x20 0xb0000000 0x0 0x10000000>; /* ECAM (256MB) */
2536 interrupt-map-mask = <0 0 0 0>;
2537 interrupt-map = <0 0 0 0 &gic GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2545 bus-range = <0x0 0xff>;
2547 …ranges = <0x43000000 0x20 0x80000000 0x20 0x80000000 0x0 0x28000000>, /* prefetchable memory (640 …
2548 …<0x02000000 0x0 0x40000000 0x20 0xa8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2549 <0x01000000 0x0 0x30100000 0x00 0x30100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2554 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE1 0x1000>;
2555 iommu-map-mask = <0x0>;
2564 reg = <0x00 0x14120000 0x0 0x00020000>, /* appl registers (128K) */
2565 <0x00 0x32000000 0x0 0x00040000>, /* configuration space (256K) */
2566 <0x00 0x32040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2567 <0x00 0x32080000 0x0 0x00040000>, /* DBI reg space (256K) */
2568 <0x20 0xf0000000 0x0 0x10000000>; /* ECAM (256MB) */
2590 interrupt-map-mask = <0 0 0 0>;
2591 interrupt-map = <0 0 0 0 &gic GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
2599 bus-range = <0x0 0xff>;
2601 …ranges = <0x43000000 0x20 0xc0000000 0x20 0xc0000000 0x0 0x28000000>, /* prefetchable memory (640 …
2602 …<0x02000000 0x0 0x40000000 0x20 0xe8000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2603 <0x01000000 0x0 0x32100000 0x00 0x32100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2608 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE2 0x1000>;
2609 iommu-map-mask = <0x0>;
2618 reg = <0x00 0x14140000 0x0 0x00020000>, /* appl registers (128K) */
2619 <0x00 0x34000000 0x0 0x00040000>, /* configuration space (256K) */
2620 <0x00 0x34040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2621 <0x00 0x34080000 0x0 0x00040000>, /* DBI reg space (256K) */
2622 <0x21 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2644 interrupt-map-mask = <0 0 0 0>;
2645 interrupt-map = <0 0 0 0 &gic GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
2653 bus-range = <0x0 0xff>;
2655 …ranges = <0x43000000 0x21 0x00000000 0x21 0x00000000 0x0 0x28000000>, /* prefetchable memory (640 …
2656 …<0x02000000 0x0 0x40000000 0x21 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2657 <0x01000000 0x0 0x34100000 0x00 0x34100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2662 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE3 0x1000>;
2663 iommu-map-mask = <0x0>;
2672 reg = <0x00 0x14160000 0x0 0x00020000>, /* appl registers (128K) */
2673 <0x00 0x36000000 0x0 0x00040000>, /* configuration space (256K) */
2674 <0x00 0x36040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2675 <0x00 0x36080000 0x0 0x00040000>, /* DBI reg space (256K) */
2676 <0x24 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2698 interrupt-map-mask = <0 0 0 0>;
2699 interrupt-map = <0 0 0 0 &gic GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
2707 bus-range = <0x0 0xff>;
2709 …ranges = <0x43000000 0x21 0x40000000 0x21 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2710 …<0x02000000 0x0 0x40000000 0x24 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2711 <0x01000000 0x0 0x36100000 0x00 0x36100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2716 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE4 0x1000>;
2717 iommu-map-mask = <0x0>;
2726 reg = <0x00 0x14180000 0x0 0x00020000>, /* appl registers (128K) */
2727 <0x00 0x38000000 0x0 0x00040000>, /* configuration space (256K) */
2728 <0x00 0x38040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2729 <0x00 0x38080000 0x0 0x00040000>, /* DBI reg space (256K) */
2730 <0x27 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2738 linux,pci-domain = <0>;
2752 interrupt-map-mask = <0 0 0 0>;
2753 interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
2755 nvidia,bpmp = <&bpmp 0>;
2761 bus-range = <0x0 0xff>;
2763 …ranges = <0x43000000 0x24 0x40000000 0x24 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2764 …<0x02000000 0x0 0x40000000 0x27 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2765 <0x01000000 0x0 0x38100000 0x00 0x38100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2770 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE0 0x1000>;
2771 iommu-map-mask = <0x0>;
2780 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2781 <0x00 0x3a000000 0x0 0x00040000>, /* configuration space (256K) */
2782 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2783 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2784 <0x2b 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2806 interrupt-map-mask = <0 0 0 0>;
2807 interrupt-map = <0 0 0 0 &gic GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2815 bus-range = <0x0 0xff>;
2817 …ranges = <0x43000000 0x28 0x00000000 0x28 0x00000000 0x3 0x28000000>, /* prefetchable memory (1292…
2818 …<0x02000000 0x0 0x40000000 0x2b 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2819 <0x01000000 0x0 0x3a100000 0x00 0x3a100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2824 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2825 iommu-map-mask = <0x0>;
2834 reg = <0x00 0x141a0000 0x0 0x00020000>, /* appl registers (128K) */
2835 <0x00 0x3a040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2836 <0x00 0x3a080000 0x0 0x00040000>, /* DBI reg space (256K) */
2837 <0x27 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
2862 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE5 0x1000>;
2863 iommu-map-mask = <0x0>;
2872 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2873 <0x00 0x3c000000 0x0 0x00040000>, /* configuration space (256K) */
2874 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2875 <0x00 0x3c080000 0x0 0x00040000>, /* DBI reg space (256K) */
2876 <0x2e 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2898 interrupt-map-mask = <0 0 0 0>;
2899 interrupt-map = <0 0 0 0 &gic GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
2907 bus-range = <0x0 0xff>;
2909 …ranges = <0x43000000 0x2b 0x40000000 0x2b 0x40000000 0x2 0xe8000000>, /* prefetchable memory (1190…
2910 …<0x02000000 0x0 0x40000000 0x2e 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
2911 <0x01000000 0x0 0x3c100000 0x00 0x3c100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
2916 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2917 iommu-map-mask = <0x0>;
2926 reg = <0x00 0x141c0000 0x0 0x00020000>, /* appl registers (128K) */
2927 <0x00 0x3c040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2928 <0x00 0x3c080000 0x0 0x00040000>, /* DBI space (256K) */
2929 <0x2b 0x40000000 0x3 0x00000000>; /* Address Space (12G) */
2954 iommu-map = <0x0 &smmu_niso0 TEGRA234_SID_PCIE6 0x1000>;
2955 iommu-map-mask = <0x0>;
2964 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
2965 <0x00 0x3e000000 0x0 0x00040000>, /* configuration space (256K) */
2966 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
2967 <0x00 0x3e080000 0x0 0x00040000>, /* DBI reg space (256K) */
2968 <0x32 0x30000000 0x0 0x10000000>; /* ECAM (256MB) */
2990 interrupt-map-mask = <0 0 0 0>;
2991 interrupt-map = <0 0 0 0 &gic GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
2999 bus-range = <0x0 0xff>;
3001 …ranges = <0x43000000 0x30 0x00000000 0x30 0x00000000 0x2 0x28000000>, /* prefetchable memory (8832…
3002 …<0x02000000 0x0 0x40000000 0x32 0x28000000 0x0 0x08000000>, /* non-prefetchable memory (128 MB) */
3003 <0x01000000 0x0 0x3e100000 0x00 0x3e100000 0x0 0x00100000>; /* downstream I/O (1 MB) */
3008 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3009 iommu-map-mask = <0x0>;
3018 reg = <0x00 0x141e0000 0x0 0x00020000>, /* appl registers (128K) */
3019 <0x00 0x3e040000 0x0 0x00040000>, /* iATU_DMA reg space (256K) */
3020 <0x00 0x3e080000 0x0 0x00040000>, /* DBI space (256K) */
3021 <0x2e 0x40000000 0x4 0x00000000>; /* Address Space (16G) */
3046 iommu-map = <0x0 &smmu_niso1 TEGRA234_SID_PCIE7 0x1000>;
3047 iommu-map-mask = <0x0>;
3056 reg = <0x0 0x40000000 0x0 0x80000>;
3060 ranges = <0x0 0x0 0x40000000 0x80000>;
3065 reg = <0x70000 0x1000>;
3071 reg = <0x71000 0x1000>;
3096 #size-cells = <0>;
3107 #size-cells = <0>;
3109 cpu0_0: cpu@0 {
3112 reg = <0x00000>;
3131 reg = <0x00100>;
3150 reg = <0x00200>;
3169 reg = <0x00300>;
3188 reg = <0x10000>;
3207 reg = <0x10100>;
3226 reg = <0x10200>;
3245 reg = <0x10300>;
3264 reg = <0x20000>;
3283 reg = <0x20100>;
3302 reg = <0x20200>;
3321 reg = <0x20300>;
3573 mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(0)>,
3588 assigned-clock-parents = <0>,