Lines Matching +full:mt8195 +full:- +full:scp_adsp
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/clock/mt8195-clk.h>
9 #include <dt-bindings/gce/mt8195-gce.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/memory/mt8195-memory-port.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
15 #include <dt-bindings/power/mt8195-power.h>
16 #include <dt-bindings/reset/mt8195-resets.h>
17 #include <dt-bindings/thermal/thermal.h>
18 #include <dt-bindings/thermal/mediatek,lvts-thermal.h>
21 compatible = "mediatek,mt8195";
22 interrupt-parent = <&gic>;
23 #address-cells = <2>;
24 #size-cells = <2>;
27 dp-intf0 = &dp_intf0;
28 dp-intf1 = &dp_intf1;
39 vdo1-rdma0 = &vdo1_rdma0;
40 vdo1-rdma1 = &vdo1_rdma1;
41 vdo1-rdma2 = &vdo1_rdma2;
42 vdo1-rdma3 = &vdo1_rdma3;
43 vdo1-rdma4 = &vdo1_rdma4;
44 vdo1-rdma5 = &vdo1_rdma5;
45 vdo1-rdma6 = &vdo1_rdma6;
46 vdo1-rdma7 = &vdo1_rdma7;
50 #address-cells = <1>;
51 #size-cells = <0>;
55 compatible = "arm,cortex-a55";
57 enable-method = "psci";
58 performance-domains = <&performance 0>;
59 clock-frequency = <1701000000>;
60 capacity-dmips-mhz = <308>;
61 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
62 i-cache-size = <32768>;
63 i-cache-line-size = <64>;
64 i-cache-sets = <128>;
65 d-cache-size = <32768>;
66 d-cache-line-size = <64>;
67 d-cache-sets = <128>;
68 next-level-cache = <&l2_0>;
69 #cooling-cells = <2>;
74 compatible = "arm,cortex-a55";
76 enable-method = "psci";
77 performance-domains = <&performance 0>;
78 clock-frequency = <1701000000>;
79 capacity-dmips-mhz = <308>;
80 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
81 i-cache-size = <32768>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <128>;
84 d-cache-size = <32768>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&l2_0>;
88 #cooling-cells = <2>;
93 compatible = "arm,cortex-a55";
95 enable-method = "psci";
96 performance-domains = <&performance 0>;
97 clock-frequency = <1701000000>;
98 capacity-dmips-mhz = <308>;
99 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
100 i-cache-size = <32768>;
101 i-cache-line-size = <64>;
102 i-cache-sets = <128>;
103 d-cache-size = <32768>;
104 d-cache-line-size = <64>;
105 d-cache-sets = <128>;
106 next-level-cache = <&l2_0>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a55";
114 enable-method = "psci";
115 performance-domains = <&performance 0>;
116 clock-frequency = <1701000000>;
117 capacity-dmips-mhz = <308>;
118 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
119 i-cache-size = <32768>;
120 i-cache-line-size = <64>;
121 i-cache-sets = <128>;
122 d-cache-size = <32768>;
123 d-cache-line-size = <64>;
124 d-cache-sets = <128>;
125 next-level-cache = <&l2_0>;
126 #cooling-cells = <2>;
131 compatible = "arm,cortex-a78";
133 enable-method = "psci";
134 performance-domains = <&performance 1>;
135 clock-frequency = <2171000000>;
136 capacity-dmips-mhz = <1024>;
137 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
138 i-cache-size = <65536>;
139 i-cache-line-size = <64>;
140 i-cache-sets = <256>;
141 d-cache-size = <65536>;
142 d-cache-line-size = <64>;
143 d-cache-sets = <256>;
144 next-level-cache = <&l2_1>;
145 #cooling-cells = <2>;
150 compatible = "arm,cortex-a78";
152 enable-method = "psci";
153 performance-domains = <&performance 1>;
154 clock-frequency = <2171000000>;
155 capacity-dmips-mhz = <1024>;
156 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
157 i-cache-size = <65536>;
158 i-cache-line-size = <64>;
159 i-cache-sets = <256>;
160 d-cache-size = <65536>;
161 d-cache-line-size = <64>;
162 d-cache-sets = <256>;
163 next-level-cache = <&l2_1>;
164 #cooling-cells = <2>;
169 compatible = "arm,cortex-a78";
171 enable-method = "psci";
172 performance-domains = <&performance 1>;
173 clock-frequency = <2171000000>;
174 capacity-dmips-mhz = <1024>;
175 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
176 i-cache-size = <65536>;
177 i-cache-line-size = <64>;
178 i-cache-sets = <256>;
179 d-cache-size = <65536>;
180 d-cache-line-size = <64>;
181 d-cache-sets = <256>;
182 next-level-cache = <&l2_1>;
183 #cooling-cells = <2>;
188 compatible = "arm,cortex-a78";
190 enable-method = "psci";
191 performance-domains = <&performance 1>;
192 clock-frequency = <2171000000>;
193 capacity-dmips-mhz = <1024>;
194 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
195 i-cache-size = <65536>;
196 i-cache-line-size = <64>;
197 i-cache-sets = <256>;
198 d-cache-size = <65536>;
199 d-cache-line-size = <64>;
200 d-cache-sets = <256>;
201 next-level-cache = <&l2_1>;
202 #cooling-cells = <2>;
205 cpu-map {
241 idle-states {
242 entry-method = "psci";
244 cpu_ret_l: cpu-retention-l {
245 compatible = "arm,idle-state";
246 arm,psci-suspend-param = <0x00010001>;
247 local-timer-stop;
248 entry-latency-us = <50>;
249 exit-latency-us = <95>;
250 min-residency-us = <580>;
253 cpu_ret_b: cpu-retention-b {
254 compatible = "arm,idle-state";
255 arm,psci-suspend-param = <0x00010001>;
256 local-timer-stop;
257 entry-latency-us = <45>;
258 exit-latency-us = <140>;
259 min-residency-us = <740>;
262 cpu_off_l: cpu-off-l {
263 compatible = "arm,idle-state";
264 arm,psci-suspend-param = <0x01010002>;
265 local-timer-stop;
266 entry-latency-us = <55>;
267 exit-latency-us = <155>;
268 min-residency-us = <840>;
271 cpu_off_b: cpu-off-b {
272 compatible = "arm,idle-state";
273 arm,psci-suspend-param = <0x01010002>;
274 local-timer-stop;
275 entry-latency-us = <50>;
276 exit-latency-us = <200>;
277 min-residency-us = <1000>;
281 l2_0: l2-cache0 {
283 cache-level = <2>;
284 cache-size = <131072>;
285 cache-line-size = <64>;
286 cache-sets = <512>;
287 next-level-cache = <&l3_0>;
288 cache-unified;
291 l2_1: l2-cache1 {
293 cache-level = <2>;
294 cache-size = <262144>;
295 cache-line-size = <64>;
296 cache-sets = <512>;
297 next-level-cache = <&l3_0>;
298 cache-unified;
301 l3_0: l3-cache {
303 cache-level = <3>;
304 cache-size = <2097152>;
305 cache-line-size = <64>;
306 cache-sets = <2048>;
307 cache-unified;
311 dsu-pmu {
312 compatible = "arm,dsu-pmu";
319 dmic_codec: dmic-codec {
320 compatible = "dmic-codec";
321 num-channels = <2>;
322 wakeup-delay-ms = <50>;
325 sound: mt8195-sound {
330 clk13m: fixed-factor-clock-13m {
331 compatible = "fixed-factor-clock";
332 #clock-cells = <0>;
334 clock-div = <2>;
335 clock-mult = <1>;
336 clock-output-names = "clk13m";
339 clk26m: oscillator-26m {
340 compatible = "fixed-clock";
341 #clock-cells = <0>;
342 clock-frequency = <26000000>;
343 clock-output-names = "clk26m";
346 clk32k: oscillator-32k {
347 compatible = "fixed-clock";
348 #clock-cells = <0>;
349 clock-frequency = <32768>;
350 clock-output-names = "clk32k";
353 performance: performance-controller@11bc10 {
354 compatible = "mediatek,cpufreq-hw";
356 #performance-domain-cells = <1>;
359 gpu_opp_table: opp-table-gpu {
360 compatible = "operating-points-v2";
361 opp-shared;
363 opp-390000000 {
364 opp-hz = /bits/ 64 <390000000>;
365 opp-microvolt = <625000>;
367 opp-410000000 {
368 opp-hz = /bits/ 64 <410000000>;
369 opp-microvolt = <631250>;
371 opp-431000000 {
372 opp-hz = /bits/ 64 <431000000>;
373 opp-microvolt = <631250>;
375 opp-473000000 {
376 opp-hz = /bits/ 64 <473000000>;
377 opp-microvolt = <637500>;
379 opp-515000000 {
380 opp-hz = /bits/ 64 <515000000>;
381 opp-microvolt = <637500>;
383 opp-556000000 {
384 opp-hz = /bits/ 64 <556000000>;
385 opp-microvolt = <643750>;
387 opp-598000000 {
388 opp-hz = /bits/ 64 <598000000>;
389 opp-microvolt = <650000>;
391 opp-640000000 {
392 opp-hz = /bits/ 64 <640000000>;
393 opp-microvolt = <650000>;
395 opp-670000000 {
396 opp-hz = /bits/ 64 <670000000>;
397 opp-microvolt = <662500>;
399 opp-700000000 {
400 opp-hz = /bits/ 64 <700000000>;
401 opp-microvolt = <675000>;
403 opp-730000000 {
404 opp-hz = /bits/ 64 <730000000>;
405 opp-microvolt = <687500>;
407 opp-760000000 {
408 opp-hz = /bits/ 64 <760000000>;
409 opp-microvolt = <700000>;
411 opp-790000000 {
412 opp-hz = /bits/ 64 <790000000>;
413 opp-microvolt = <712500>;
415 opp-820000000 {
416 opp-hz = /bits/ 64 <820000000>;
417 opp-microvolt = <725000>;
419 opp-850000000 {
420 opp-hz = /bits/ 64 <850000000>;
421 opp-microvolt = <737500>;
423 opp-880000000 {
424 opp-hz = /bits/ 64 <880000000>;
425 opp-microvolt = <750000>;
429 pmu-a55 {
430 compatible = "arm,cortex-a55-pmu";
431 interrupt-parent = <&gic>;
435 pmu-a78 {
436 compatible = "arm,cortex-a78-pmu";
437 interrupt-parent = <&gic>;
442 compatible = "arm,psci-1.0";
447 compatible = "arm,armv8-timer";
448 interrupt-parent = <&gic>;
456 #address-cells = <2>;
457 #size-cells = <2>;
458 compatible = "simple-bus";
460 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
462 gic: interrupt-controller@c000000 {
463 compatible = "arm,gic-v3";
464 #interrupt-cells = <4>;
465 #redistributor-regions = <1>;
466 interrupt-parent = <&gic>;
467 interrupt-controller;
472 ppi-partitions {
473 ppi_cluster0: interrupt-partition-0 {
477 ppi_cluster1: interrupt-partition-1 {
484 compatible = "mediatek,mt8195-topckgen", "syscon";
486 #clock-cells = <1>;
490 compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
492 #clock-cells = <1>;
493 #reset-cells = <1>;
497 compatible = "mediatek,mt8195-pericfg", "syscon";
499 #clock-cells = <1>;
503 compatible = "mediatek,mt8195-pinctrl";
512 reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
515 gpio-controller;
516 #gpio-cells = <2>;
517 gpio-ranges = <&pio 0 0 144>;
518 interrupt-controller;
520 #interrupt-cells = <2>;
524 compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
528 spm: power-controller {
529 compatible = "mediatek,mt8195-power-controller";
530 #address-cells = <1>;
531 #size-cells = <0>;
532 #power-domain-cells = <1>;
535 mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
537 #address-cells = <1>;
538 #size-cells = <0>;
539 #power-domain-cells = <1>;
541 power-domain@MT8195_POWER_DOMAIN_MFG1 {
545 clock-names = "mfg", "alt";
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <1>;
551 power-domain@MT8195_POWER_DOMAIN_MFG2 {
553 #power-domain-cells = <0>;
556 power-domain@MT8195_POWER_DOMAIN_MFG3 {
558 #power-domain-cells = <0>;
561 power-domain@MT8195_POWER_DOMAIN_MFG4 {
563 #power-domain-cells = <0>;
566 power-domain@MT8195_POWER_DOMAIN_MFG5 {
568 #power-domain-cells = <0>;
571 power-domain@MT8195_POWER_DOMAIN_MFG6 {
573 #power-domain-cells = <0>;
578 power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
607 clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
609 "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
610 "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
611 "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
612 "vppsys0-12", "vppsys0-13", "vppsys0-14",
613 "vppsys0-15", "vppsys0-16", "vppsys0-17",
614 "vppsys0-18";
616 #address-cells = <1>;
617 #size-cells = <0>;
618 #power-domain-cells = <1>;
620 power-domain@MT8195_POWER_DOMAIN_VDEC1 {
623 clock-names = "vdec1-0";
625 #power-domain-cells = <0>;
628 power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
631 #power-domain-cells = <0>;
634 power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
643 clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
644 "vdosys0-2", "vdosys0-3",
645 "vdosys0-4", "vdosys0-5";
647 #address-cells = <1>;
648 #size-cells = <0>;
649 #power-domain-cells = <1>;
651 power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
656 clock-names = "vppsys1", "vppsys1-0",
657 "vppsys1-1";
659 #power-domain-cells = <0>;
662 power-domain@MT8195_POWER_DOMAIN_WPESYS {
668 clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
669 "wepsys-3";
671 #power-domain-cells = <0>;
674 power-domain@MT8195_POWER_DOMAIN_VDEC0 {
677 clock-names = "vdec0-0";
679 #power-domain-cells = <0>;
682 power-domain@MT8195_POWER_DOMAIN_VDEC2 {
685 clock-names = "vdec2-0";
687 #power-domain-cells = <0>;
690 power-domain@MT8195_POWER_DOMAIN_VENC {
693 #power-domain-cells = <0>;
696 power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
702 clock-names = "vdosys1", "vdosys1-0",
703 "vdosys1-1", "vdosys1-2";
705 #address-cells = <1>;
706 #size-cells = <0>;
707 #power-domain-cells = <1>;
709 power-domain@MT8195_POWER_DOMAIN_DP_TX {
712 #power-domain-cells = <0>;
715 power-domain@MT8195_POWER_DOMAIN_EPD_TX {
718 #power-domain-cells = <0>;
721 power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
724 clock-names = "hdmi_tx";
725 #power-domain-cells = <0>;
729 power-domain@MT8195_POWER_DOMAIN_IMG {
733 clock-names = "img-0", "img-1";
735 #address-cells = <1>;
736 #size-cells = <0>;
737 #power-domain-cells = <1>;
739 power-domain@MT8195_POWER_DOMAIN_DIP {
741 #power-domain-cells = <0>;
744 power-domain@MT8195_POWER_DOMAIN_IPE {
749 clock-names = "ipe", "ipe-0", "ipe-1";
751 #power-domain-cells = <0>;
755 power-domain@MT8195_POWER_DOMAIN_CAM {
762 clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
763 "cam-4";
765 #address-cells = <1>;
766 #size-cells = <0>;
767 #power-domain-cells = <1>;
769 power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
771 #power-domain-cells = <0>;
774 power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
776 #power-domain-cells = <0>;
779 power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
781 #power-domain-cells = <0>;
787 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
790 #power-domain-cells = <0>;
793 power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
796 #power-domain-cells = <0>;
799 power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
801 #power-domain-cells = <0>;
804 power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
806 #power-domain-cells = <0>;
809 power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
813 clock-names = "csi_rx_top", "csi_rx_top1";
814 #power-domain-cells = <0>;
817 power-domain@MT8195_POWER_DOMAIN_ETHER {
820 clock-names = "ether";
821 #power-domain-cells = <0>;
824 power-domain@MT8195_POWER_DOMAIN_ADSP {
828 clock-names = "adsp", "adsp1";
829 #address-cells = <1>;
830 #size-cells = <0>;
832 #power-domain-cells = <1>;
834 power-domain@MT8195_POWER_DOMAIN_AUDIO {
840 clock-names = "audio", "audio1", "audio2",
843 #power-domain-cells = <0>;
850 compatible = "mediatek,mt8195-wdt";
851 mediatek,disable-extrst;
853 #reset-cells = <1>;
857 compatible = "mediatek,mt8195-apmixedsys", "syscon";
859 #clock-cells = <1>;
863 compatible = "mediatek,mt8195-timer",
864 "mediatek,mt6765-timer";
871 compatible = "mediatek,mt8195-pwrap", "syscon";
873 reg-names = "pwrap";
877 clock-names = "spi", "wrap";
878 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
879 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
883 compatible = "mediatek,mt8195-spmi";
886 reg-names = "pmif", "spmimst";
890 clock-names = "pmif_sys_ck",
893 assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
894 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
897 iommu_infra: infra-iommu@10315000 {
898 compatible = "mediatek,mt8195-iommu-infra";
905 #iommu-cells = <1>;
909 compatible = "mediatek,mt8195-gce";
912 #mbox-cells = <2>;
917 compatible = "mediatek,mt8195-gce";
920 #mbox-cells = <2>;
925 compatible = "mediatek,mt8195-scp";
929 reg-names = "sram", "cfg", "l1tcm";
934 scp_adsp: clock-controller@10720000 { label
935 compatible = "mediatek,mt8195-scp_adsp";
937 #clock-cells = <1>;
941 compatible = "mediatek,mt8195-dsp";
944 reg-names = "cfg", "sram";
949 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
951 clock-names = "adsp_sel",
957 power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
958 mbox-names = "rx", "tx";
964 compatible = "mediatek,mt8195-adsp-mbox";
965 #mbox-cells = <0>;
971 compatible = "mediatek,mt8195-adsp-mbox";
972 #mbox-cells = <0>;
977 afe: mt8195-afe-pcm@10890000 {
978 compatible = "mediatek,mt8195-audio";
981 power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
984 reset-names = "audiosys";
1003 <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
1004 clock-names = "clk26m",
1027 compatible = "mediatek,mt8195-uart",
1028 "mediatek,mt6577-uart";
1032 clock-names = "baud", "bus";
1037 compatible = "mediatek,mt8195-uart",
1038 "mediatek,mt6577-uart";
1042 clock-names = "baud", "bus";
1047 compatible = "mediatek,mt8195-uart",
1048 "mediatek,mt6577-uart";
1052 clock-names = "baud", "bus";
1057 compatible = "mediatek,mt8195-uart",
1058 "mediatek,mt6577-uart";
1062 clock-names = "baud", "bus";
1067 compatible = "mediatek,mt8195-uart",
1068 "mediatek,mt6577-uart";
1072 clock-names = "baud", "bus";
1077 compatible = "mediatek,mt8195-uart",
1078 "mediatek,mt6577-uart";
1082 clock-names = "baud", "bus";
1087 compatible = "mediatek,mt8195-auxadc",
1088 "mediatek,mt8173-auxadc";
1091 clock-names = "main";
1092 #io-channel-cells = <1>;
1097 compatible = "mediatek,mt8195-pericfg_ao", "syscon";
1099 #clock-cells = <1>;
1103 compatible = "mediatek,mt8195-spi",
1104 "mediatek,mt6765-spi";
1105 #address-cells = <1>;
1106 #size-cells = <0>;
1112 clock-names = "parent-clk", "sel-clk", "spi-clk";
1116 lvts_ap: thermal-sensor@1100b000 {
1117 compatible = "mediatek,mt8195-lvts-ap";
1122 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1123 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1124 #thermal-sensor-cells = <1>;
1128 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1131 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
1132 #pwm-cells = <2>;
1135 clock-names = "main", "mm";
1140 compatible = "mediatek,mt8195-disp-pwm", "mediatek,mt8183-disp-pwm";
1143 #pwm-cells = <2>;
1146 clock-names = "main", "mm";
1151 compatible = "mediatek,mt8195-spi",
1152 "mediatek,mt6765-spi";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1160 clock-names = "parent-clk", "sel-clk", "spi-clk";
1165 compatible = "mediatek,mt8195-spi",
1166 "mediatek,mt6765-spi";
1167 #address-cells = <1>;
1168 #size-cells = <0>;
1174 clock-names = "parent-clk", "sel-clk", "spi-clk";
1179 compatible = "mediatek,mt8195-spi",
1180 "mediatek,mt6765-spi";
1181 #address-cells = <1>;
1182 #size-cells = <0>;
1188 clock-names = "parent-clk", "sel-clk", "spi-clk";
1193 compatible = "mediatek,mt8195-spi",
1194 "mediatek,mt6765-spi";
1195 #address-cells = <1>;
1196 #size-cells = <0>;
1202 clock-names = "parent-clk", "sel-clk", "spi-clk";
1207 compatible = "mediatek,mt8195-spi",
1208 "mediatek,mt6765-spi";
1209 #address-cells = <1>;
1210 #size-cells = <0>;
1216 clock-names = "parent-clk", "sel-clk", "spi-clk";
1221 compatible = "mediatek,mt8195-spi-slave";
1225 clock-names = "spi";
1226 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1227 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1232 compatible = "mediatek,mt8195-spi-slave";
1236 clock-names = "spi";
1237 assigned-clocks = <&topckgen CLK_TOP_SPIS>;
1238 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
1243 compatible = "mediatek,mt8195-gmac", "snps,dwmac-5.10a";
1246 interrupt-names = "macirq";
1247 clock-names = "axi",
1259 assigned-clocks = <&topckgen CLK_TOP_SNPS_ETH_250M>,
1262 assigned-clock-parents = <&topckgen CLK_TOP_ETHPLL_D2>,
1265 power-domains = <&spm MT8195_POWER_DOMAIN_ETHER>;
1267 snps,axi-config = <&stmmac_axi_setup>;
1268 snps,mtl-rx-config = <&mtl_rx_setup>;
1269 snps,mtl-tx-config = <&mtl_tx_setup>;
1272 snps,clk-csr = <0>;
1276 compatible = "snps,dwmac-mdio";
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1281 stmmac_axi_setup: stmmac-axi-config {
1287 mtl_rx_setup: rx-queues-config {
1288 snps,rx-queues-to-use = <4>;
1289 snps,rx-sched-sp;
1291 snps,dcb-algorithm;
1292 snps,map-to-dma-channel = <0x0>;
1295 snps,dcb-algorithm;
1296 snps,map-to-dma-channel = <0x0>;
1299 snps,dcb-algorithm;
1300 snps,map-to-dma-channel = <0x0>;
1303 snps,dcb-algorithm;
1304 snps,map-to-dma-channel = <0x0>;
1308 mtl_tx_setup: tx-queues-config {
1309 snps,tx-queues-to-use = <4>;
1310 snps,tx-sched-wrr;
1313 snps,dcb-algorithm;
1318 snps,dcb-algorithm;
1323 snps,dcb-algorithm;
1328 snps,dcb-algorithm;
1335 compatible = "mediatek,mt8195-xhci",
1336 "mediatek,mtk-xhci";
1339 reg-names = "mac", "ippc";
1343 assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
1345 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1352 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1354 mediatek,syscon-wakeup = <&pericfg 0x400 103>;
1355 wakeup-source;
1360 compatible = "mediatek,mt8195-mmc",
1361 "mediatek,mt8183-mmc";
1368 clock-names = "source", "hclk", "source_cg";
1373 compatible = "mediatek,mt8195-mmc",
1374 "mediatek,mt8183-mmc";
1381 clock-names = "source", "hclk", "source_cg";
1382 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1383 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1388 compatible = "mediatek,mt8195-mmc",
1389 "mediatek,mt8183-mmc";
1396 clock-names = "source", "hclk", "source_cg";
1397 assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
1398 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1402 lvts_mcu: thermal-sensor@11278000 {
1403 compatible = "mediatek,mt8195-lvts-mcu";
1408 nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>;
1409 nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2";
1410 #thermal-sensor-cells = <1>;
1414 compatible = "mediatek,mt8195-xhci",
1415 "mediatek,mtk-xhci";
1418 reg-names = "mac", "ippc";
1421 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
1423 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1430 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1432 mediatek,syscon-wakeup = <&pericfg 0x400 104>;
1433 wakeup-source;
1438 compatible = "mediatek,mt8195-xhci",
1439 "mediatek,mtk-xhci";
1442 reg-names = "mac", "ippc";
1445 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
1447 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1454 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1456 mediatek,syscon-wakeup = <&pericfg 0x400 105>;
1457 wakeup-source;
1462 compatible = "mediatek,mt8195-xhci",
1463 "mediatek,mtk-xhci";
1466 reg-names = "mac", "ippc";
1469 assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
1471 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
1478 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck",
1480 mediatek,syscon-wakeup = <&pericfg 0x400 106>;
1481 wakeup-source;
1486 compatible = "mediatek,mt8195-pcie",
1487 "mediatek,mt8192-pcie";
1489 #address-cells = <3>;
1490 #size-cells = <2>;
1492 reg-names = "pcie-mac";
1494 bus-range = <0x00 0xff>;
1500 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE0 0x2>;
1501 iommu-map-mask = <0x0>;
1509 clock-names = "pl_250m", "tl_26m", "tl_96m",
1511 assigned-clocks = <&topckgen CLK_TOP_TL>;
1512 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1515 phy-names = "pcie-phy";
1517 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
1520 reset-names = "mac";
1522 #interrupt-cells = <1>;
1523 interrupt-map-mask = <0 0 0 7>;
1524 interrupt-map = <0 0 0 1 &pcie_intc0 0>,
1530 pcie_intc0: interrupt-controller {
1531 interrupt-controller;
1532 #address-cells = <0>;
1533 #interrupt-cells = <1>;
1538 compatible = "mediatek,mt8195-pcie",
1539 "mediatek,mt8192-pcie";
1541 #address-cells = <3>;
1542 #size-cells = <2>;
1544 reg-names = "pcie-mac";
1546 bus-range = <0x00 0xff>;
1552 iommu-map = <0 &iommu_infra IOMMU_PORT_INFRA_PCIE1 0x2>;
1553 iommu-map-mask = <0x0>;
1562 clock-names = "pl_250m", "tl_26m", "tl_96m",
1564 assigned-clocks = <&topckgen CLK_TOP_TL_P1>;
1565 assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4_D4>;
1568 phy-names = "pcie-phy";
1569 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
1572 reset-names = "mac";
1574 #interrupt-cells = <1>;
1575 interrupt-map-mask = <0 0 0 7>;
1576 interrupt-map = <0 0 0 1 &pcie_intc1 0>,
1582 pcie_intc1: interrupt-controller {
1583 interrupt-controller;
1584 #address-cells = <0>;
1585 #interrupt-cells = <1>;
1590 compatible = "mediatek,mt8195-nor",
1591 "mediatek,mt8173-nor";
1597 clock-names = "spi", "sf", "axi";
1598 #address-cells = <1>;
1599 #size-cells = <0>;
1604 compatible = "mediatek,mt8195-efuse", "mediatek,efuse";
1606 #address-cells = <1>;
1607 #size-cells = <1>;
1608 u3_tx_imp_p0: usb3-tx-imp@184,1 {
1612 u3_rx_imp_p0: usb3-rx-imp@184,2 {
1616 u3_intr_p0: usb3-intr@185 {
1620 comb_tx_imp_p1: usb3-tx-imp@186,1 {
1624 comb_rx_imp_p1: usb3-rx-imp@186,2 {
1628 comb_intr_p1: usb3-intr@187 {
1632 u2_intr_p0: usb2-intr-p0@188,1 {
1636 u2_intr_p1: usb2-intr-p1@188,2 {
1640 u2_intr_p2: usb2-intr-p2@189,1 {
1644 u2_intr_p3: usb2-intr-p3@189,2 {
1648 pciephy_rx_ln1: pciephy-rx-ln1@190,1 {
1652 pciephy_tx_ln1_nmos: pciephy-tx-ln1-nmos@190,2 {
1656 pciephy_tx_ln1_pmos: pciephy-tx-ln1-pmos@191,1 {
1660 pciephy_rx_ln0: pciephy-rx-ln0@191,2 {
1664 pciephy_tx_ln0_nmos: pciephy-tx-ln0-nmos@192,1 {
1668 pciephy_tx_ln0_pmos: pciephy-tx-ln0-pmos@192,2 {
1672 pciephy_glb_intr: pciephy-glb-intr@193 {
1676 dp_calibration: dp-data@1ac {
1679 lvts_efuse_data1: lvts1-calib@1bc {
1682 lvts_efuse_data2: lvts2-calib@1d0 {
1687 u3phy2: t-phy@11c40000 {
1688 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1689 #address-cells = <1>;
1690 #size-cells = <1>;
1694 u2port2: usb-phy@0 {
1697 clock-names = "ref";
1698 #phy-cells = <1>;
1702 u3phy3: t-phy@11c50000 {
1703 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1704 #address-cells = <1>;
1705 #size-cells = <1>;
1709 u2port3: usb-phy@0 {
1712 clock-names = "ref";
1713 #phy-cells = <1>;
1718 compatible = "mediatek,mt8195-i2c",
1719 "mediatek,mt8192-i2c";
1723 clock-div = <1>;
1726 clock-names = "main", "dma";
1727 #address-cells = <1>;
1728 #size-cells = <0>;
1733 compatible = "mediatek,mt8195-i2c",
1734 "mediatek,mt8192-i2c";
1738 clock-div = <1>;
1741 clock-names = "main", "dma";
1742 #address-cells = <1>;
1743 #size-cells = <0>;
1748 compatible = "mediatek,mt8195-i2c",
1749 "mediatek,mt8192-i2c";
1753 clock-div = <1>;
1756 clock-names = "main", "dma";
1757 #address-cells = <1>;
1758 #size-cells = <0>;
1762 imp_iic_wrap_s: clock-controller@11d03000 {
1763 compatible = "mediatek,mt8195-imp_iic_wrap_s";
1765 #clock-cells = <1>;
1769 compatible = "mediatek,mt8195-i2c",
1770 "mediatek,mt8192-i2c";
1774 clock-div = <1>;
1777 clock-names = "main", "dma";
1778 #address-cells = <1>;
1779 #size-cells = <0>;
1784 compatible = "mediatek,mt8195-i2c",
1785 "mediatek,mt8192-i2c";
1789 clock-div = <1>;
1792 clock-names = "main", "dma";
1793 #address-cells = <1>;
1794 #size-cells = <0>;
1799 compatible = "mediatek,mt8195-i2c",
1800 "mediatek,mt8192-i2c";
1804 clock-div = <1>;
1807 clock-names = "main", "dma";
1808 #address-cells = <1>;
1809 #size-cells = <0>;
1814 compatible = "mediatek,mt8195-i2c",
1815 "mediatek,mt8192-i2c";
1819 clock-div = <1>;
1822 clock-names = "main", "dma";
1823 #address-cells = <1>;
1824 #size-cells = <0>;
1829 compatible = "mediatek,mt8195-i2c",
1830 "mediatek,mt8192-i2c";
1834 clock-div = <1>;
1837 clock-names = "main", "dma";
1838 #address-cells = <1>;
1839 #size-cells = <0>;
1843 imp_iic_wrap_w: clock-controller@11e05000 {
1844 compatible = "mediatek,mt8195-imp_iic_wrap_w";
1846 #clock-cells = <1>;
1849 u3phy1: t-phy@11e30000 {
1850 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1851 #address-cells = <1>;
1852 #size-cells = <1>;
1854 power-domains = <&spm MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
1857 u2port1: usb-phy@0 {
1861 clock-names = "ref", "da_ref";
1862 #phy-cells = <1>;
1865 u3port1: usb-phy@700 {
1869 clock-names = "ref", "da_ref";
1870 nvmem-cells = <&comb_intr_p1>,
1873 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1874 #phy-cells = <1>;
1878 u3phy0: t-phy@11e40000 {
1879 compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
1880 #address-cells = <1>;
1881 #size-cells = <1>;
1885 u2port0: usb-phy@0 {
1889 clock-names = "ref", "da_ref";
1890 #phy-cells = <1>;
1893 u3port0: usb-phy@700 {
1897 clock-names = "ref", "da_ref";
1898 nvmem-cells = <&u3_intr_p0>,
1901 nvmem-cell-names = "intr", "rx_imp", "tx_imp";
1902 #phy-cells = <1>;
1907 compatible = "mediatek,mt8195-pcie-phy";
1909 reg-names = "sif";
1910 nvmem-cells = <&pciephy_glb_intr>, <&pciephy_tx_ln0_pmos>,
1914 nvmem-cell-names = "glb_intr", "tx_ln0_pmos",
1918 power-domains = <&spm MT8195_POWER_DOMAIN_PCIE_PHY>;
1919 #phy-cells = <0>;
1923 ufsphy: ufs-phy@11fa0000 {
1924 compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
1927 clock-names = "unipro", "mp";
1928 #phy-cells = <0>;
1933 compatible = "mediatek,mt8195-mali", "mediatek,mt8192-mali",
1934 "arm,mali-valhall-jm";
1941 interrupt-names = "job", "mmu", "gpu";
1942 operating-points-v2 = <&gpu_opp_table>;
1943 power-domains = <&spm MT8195_POWER_DOMAIN_MFG2>,
1948 power-domain-names = "core0", "core1", "core2", "core3", "core4";
1952 mfgcfg: clock-controller@13fbf000 {
1953 compatible = "mediatek,mt8195-mfgcfg";
1955 #clock-cells = <1>;
1959 compatible = "mediatek,mt8195-vppsys0", "syscon";
1961 #clock-cells = <1>;
1965 compatible = "mediatek,mt8195-vpp-mutex";
1968 mediatek,gce-client-reg = <&gce1 SUBSYS_1400XXXX 0xf000 0x1000>;
1970 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1974 compatible = "mediatek,mt8195-smi-sub-common";
1979 clock-names = "apb", "smi", "gals0";
1981 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1985 compatible = "mediatek,mt8195-smi-sub-common";
1990 clock-names = "apb", "smi", "gals0";
1992 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
1996 compatible = "mediatek,mt8195-smi-common-vpp";
2002 clock-names = "apb", "smi", "gals0", "gals1";
2003 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2007 compatible = "mediatek,mt8195-smi-larb";
2009 mediatek,larb-id = <4>;
2013 clock-names = "apb", "smi";
2014 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2018 compatible = "mediatek,mt8195-iommu-vpp";
2026 clock-names = "bclk";
2027 #iommu-cells = <1>;
2028 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
2031 wpesys: clock-controller@14e00000 {
2032 compatible = "mediatek,mt8195-wpesys";
2034 #clock-cells = <1>;
2037 wpesys_vpp0: clock-controller@14e02000 {
2038 compatible = "mediatek,mt8195-wpesys_vpp0";
2040 #clock-cells = <1>;
2043 wpesys_vpp1: clock-controller@14e03000 {
2044 compatible = "mediatek,mt8195-wpesys_vpp1";
2046 #clock-cells = <1>;
2050 compatible = "mediatek,mt8195-smi-larb";
2052 mediatek,larb-id = <7>;
2056 clock-names = "apb", "smi";
2057 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2061 compatible = "mediatek,mt8195-smi-larb";
2063 mediatek,larb-id = <8>;
2068 clock-names = "apb", "smi", "gals";
2069 power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
2073 compatible = "mediatek,mt8195-vppsys1", "syscon";
2075 #clock-cells = <1>;
2079 compatible = "mediatek,mt8195-vpp-mutex";
2082 mediatek,gce-client-reg = <&gce1 SUBSYS_14f0XXXX 0x1000 0x1000>;
2084 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2088 compatible = "mediatek,mt8195-smi-larb";
2090 mediatek,larb-id = <5>;
2095 clock-names = "apb", "smi", "gals";
2096 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2100 compatible = "mediatek,mt8195-smi-larb";
2102 mediatek,larb-id = <6>;
2107 clock-names = "apb", "smi", "gals";
2108 power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
2111 imgsys: clock-controller@15000000 {
2112 compatible = "mediatek,mt8195-imgsys";
2114 #clock-cells = <1>;
2118 compatible = "mediatek,mt8195-smi-larb";
2120 mediatek,larb-id = <9>;
2125 clock-names = "apb", "smi", "gals";
2126 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2130 compatible = "mediatek,mt8195-smi-sub-common";
2135 clock-names = "apb", "smi", "gals0";
2137 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2141 compatible = "mediatek,mt8195-smi-sub-common";
2146 clock-names = "apb", "smi", "gals0";
2148 power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
2151 imgsys1_dip_top: clock-controller@15110000 {
2152 compatible = "mediatek,mt8195-imgsys1_dip_top";
2154 #clock-cells = <1>;
2158 compatible = "mediatek,mt8195-smi-larb";
2160 mediatek,larb-id = <10>;
2164 clock-names = "apb", "smi";
2165 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2168 imgsys1_dip_nr: clock-controller@15130000 {
2169 compatible = "mediatek,mt8195-imgsys1_dip_nr";
2171 #clock-cells = <1>;
2174 imgsys1_wpe: clock-controller@15220000 {
2175 compatible = "mediatek,mt8195-imgsys1_wpe";
2177 #clock-cells = <1>;
2181 compatible = "mediatek,mt8195-smi-larb";
2183 mediatek,larb-id = <11>;
2187 clock-names = "apb", "smi";
2188 power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
2191 ipesys: clock-controller@15330000 {
2192 compatible = "mediatek,mt8195-ipesys";
2194 #clock-cells = <1>;
2198 compatible = "mediatek,mt8195-smi-larb";
2200 mediatek,larb-id = <12>;
2204 clock-names = "apb", "smi";
2205 power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
2208 camsys: clock-controller@16000000 {
2209 compatible = "mediatek,mt8195-camsys";
2211 #clock-cells = <1>;
2215 compatible = "mediatek,mt8195-smi-larb";
2217 mediatek,larb-id = <13>;
2222 clock-names = "apb", "smi", "gals";
2223 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2227 compatible = "mediatek,mt8195-smi-larb";
2229 mediatek,larb-id = <14>;
2233 clock-names = "apb", "smi";
2234 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2238 compatible = "mediatek,mt8195-smi-sub-common";
2243 clock-names = "apb", "smi", "gals0";
2245 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2249 compatible = "mediatek,mt8195-smi-sub-common";
2254 clock-names = "apb", "smi", "gals0";
2256 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2260 compatible = "mediatek,mt8195-smi-larb";
2262 mediatek,larb-id = <16>;
2266 clock-names = "apb", "smi";
2267 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2271 compatible = "mediatek,mt8195-smi-larb";
2273 mediatek,larb-id = <17>;
2277 clock-names = "apb", "smi";
2278 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
2282 compatible = "mediatek,mt8195-smi-larb";
2284 mediatek,larb-id = <27>;
2288 clock-names = "apb", "smi";
2289 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2293 compatible = "mediatek,mt8195-smi-larb";
2295 mediatek,larb-id = <28>;
2299 clock-names = "apb", "smi";
2300 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
2303 camsys_rawa: clock-controller@1604f000 {
2304 compatible = "mediatek,mt8195-camsys_rawa";
2306 #clock-cells = <1>;
2309 camsys_yuva: clock-controller@1606f000 {
2310 compatible = "mediatek,mt8195-camsys_yuva";
2312 #clock-cells = <1>;
2315 camsys_rawb: clock-controller@1608f000 {
2316 compatible = "mediatek,mt8195-camsys_rawb";
2318 #clock-cells = <1>;
2321 camsys_yuvb: clock-controller@160af000 {
2322 compatible = "mediatek,mt8195-camsys_yuvb";
2324 #clock-cells = <1>;
2327 camsys_mraw: clock-controller@16140000 {
2328 compatible = "mediatek,mt8195-camsys_mraw";
2330 #clock-cells = <1>;
2334 compatible = "mediatek,mt8195-smi-larb";
2336 mediatek,larb-id = <25>;
2341 clock-names = "apb", "smi", "gals";
2342 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2346 compatible = "mediatek,mt8195-smi-larb";
2348 mediatek,larb-id = <26>;
2352 clock-names = "apb", "smi";
2353 power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
2357 ccusys: clock-controller@17200000 {
2358 compatible = "mediatek,mt8195-ccusys";
2360 #clock-cells = <1>;
2364 compatible = "mediatek,mt8195-smi-larb";
2366 mediatek,larb-id = <18>;
2370 clock-names = "apb", "smi";
2371 power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
2374 video-codec@18000000 {
2375 compatible = "mediatek,mt8195-vcodec-dec";
2378 #address-cells = <2>;
2379 #size-cells = <2>;
2384 video-codec@2000 {
2385 compatible = "mediatek,mtk-vcodec-lat-soc";
2393 clock-names = "sel", "vdec", "lat", "top";
2394 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2395 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2396 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2399 video-codec@10000 {
2400 compatible = "mediatek,mtk-vcodec-lat";
2413 clock-names = "sel", "vdec", "lat", "top";
2414 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2415 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2416 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2419 video-codec@25000 {
2420 compatible = "mediatek,mtk-vcodec-core";
2437 clock-names = "sel", "vdec", "lat", "top";
2438 assigned-clocks = <&topckgen CLK_TOP_VDEC>;
2439 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2440 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2445 compatible = "mediatek,mt8195-smi-larb";
2447 mediatek,larb-id = <24>;
2451 clock-names = "apb", "smi";
2452 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2456 compatible = "mediatek,mt8195-smi-larb";
2458 mediatek,larb-id = <23>;
2462 clock-names = "apb", "smi";
2463 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2466 vdecsys_soc: clock-controller@1800f000 {
2467 compatible = "mediatek,mt8195-vdecsys_soc";
2469 #clock-cells = <1>;
2473 compatible = "mediatek,mt8195-smi-larb";
2475 mediatek,larb-id = <21>;
2479 clock-names = "apb", "smi";
2480 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2483 vdecsys: clock-controller@1802f000 {
2484 compatible = "mediatek,mt8195-vdecsys";
2486 #clock-cells = <1>;
2490 compatible = "mediatek,mt8195-smi-larb";
2492 mediatek,larb-id = <22>;
2496 clock-names = "apb", "smi";
2497 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2500 vdecsys_core1: clock-controller@1803f000 {
2501 compatible = "mediatek,mt8195-vdecsys_core1";
2503 #clock-cells = <1>;
2506 apusys_pll: clock-controller@190f3000 {
2507 compatible = "mediatek,mt8195-apusys_pll";
2509 #clock-cells = <1>;
2512 vencsys: clock-controller@1a000000 {
2513 compatible = "mediatek,mt8195-vencsys";
2515 #clock-cells = <1>;
2519 compatible = "mediatek,mt8195-smi-larb";
2521 mediatek,larb-id = <19>;
2525 clock-names = "apb", "smi";
2526 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2529 venc: video-codec@1a020000 {
2530 compatible = "mediatek,mt8195-vcodec-enc";
2544 clock-names = "venc_sel";
2545 assigned-clocks = <&topckgen CLK_TOP_VENC>;
2546 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
2547 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2548 #address-cells = <2>;
2549 #size-cells = <2>;
2552 jpgdec-master {
2553 compatible = "mediatek,mt8195-jpgdec";
2554 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2561 #address-cells = <2>;
2562 #size-cells = <2>;
2566 compatible = "mediatek,mt8195-jpgdec-hw";
2576 clock-names = "jpgdec";
2577 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
2581 compatible = "mediatek,mt8195-jpgdec-hw";
2591 clock-names = "jpgdec";
2592 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
2596 compatible = "mediatek,mt8195-jpgdec-hw";
2606 clock-names = "jpgdec";
2607 power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
2611 vencsys_core1: clock-controller@1b000000 {
2612 compatible = "mediatek,mt8195-vencsys_core1";
2614 #clock-cells = <1>;
2618 compatible = "mediatek,mt8195-vdosys0", "mediatek,mt8195-mmsys", "syscon";
2621 #clock-cells = <1>;
2625 jpgenc-master {
2626 compatible = "mediatek,mt8195-jpgenc";
2627 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2632 #address-cells = <2>;
2633 #size-cells = <2>;
2637 compatible = "mediatek,mt8195-jpgenc-hw";
2645 clock-names = "jpgenc";
2646 power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
2650 compatible = "mediatek,mt8195-jpgenc-hw";
2658 clock-names = "jpgenc";
2659 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2664 compatible = "mediatek,mt8195-smi-larb";
2666 mediatek,larb-id = <20>;
2671 clock-names = "apb", "smi", "gals";
2672 power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
2676 compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
2679 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2682 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
2686 compatible = "mediatek,mt8195-disp-rdma";
2689 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2692 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
2696 compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
2699 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2701 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
2705 compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
2708 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2710 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
2714 compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
2717 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2719 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
2723 compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
2726 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2728 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
2732 compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
2735 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2737 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
2741 compatible = "mediatek,mt8195-disp-dsc";
2744 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2746 mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
2750 compatible = "mediatek,mt8195-disp-merge";
2753 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2755 mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
2758 dp_intf0: dp-intf@1c015000 {
2759 compatible = "mediatek,mt8195-dp-intf";
2765 clock-names = "engine", "pixel", "pll";
2770 compatible = "mediatek,mt8195-disp-mutex";
2773 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2775 mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
2779 compatible = "mediatek,mt8195-smi-larb";
2781 mediatek,larb-id = <0>;
2786 clock-names = "apb", "smi", "gals";
2787 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2791 compatible = "mediatek,mt8195-smi-larb";
2793 mediatek,larb-id = <1>;
2798 clock-names = "apb", "smi", "gals";
2799 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2803 compatible = "mediatek,mt8195-vdosys1", "syscon";
2806 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x0000 0x1000>;
2807 #clock-cells = <1>;
2808 #reset-cells = <1>;
2812 compatible = "mediatek,mt8195-smi-common-vdo";
2818 clock-names = "apb", "smi", "gals0", "gals1";
2819 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2824 compatible = "mediatek,mt8195-iommu-vdo";
2831 #iommu-cells = <1>;
2833 clock-names = "bclk";
2834 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
2838 compatible = "mediatek,mt8195-disp-mutex";
2840 reg-names = "vdo1_mutex";
2842 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2844 clock-names = "vdo1_mutex";
2845 mediatek,gce-events = <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
2849 compatible = "mediatek,mt8195-smi-larb";
2851 mediatek,larb-id = <2>;
2856 clock-names = "apb", "smi", "gals";
2857 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2861 compatible = "mediatek,mt8195-smi-larb";
2863 mediatek,larb-id = <3>;
2868 clock-names = "apb", "smi", "gals";
2869 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2873 compatible = "mediatek,mt8195-vdo1-rdma";
2877 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2879 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x4000 0x1000>;
2883 compatible = "mediatek,mt8195-vdo1-rdma";
2887 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2889 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x5000 0x1000>;
2893 compatible = "mediatek,mt8195-vdo1-rdma";
2897 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2899 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x6000 0x1000>;
2903 compatible = "mediatek,mt8195-vdo1-rdma";
2907 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2909 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x7000 0x1000>;
2913 compatible = "mediatek,mt8195-vdo1-rdma";
2917 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2919 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x8000 0x1000>;
2923 compatible = "mediatek,mt8195-vdo1-rdma";
2927 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2929 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0x9000 0x1000>;
2933 compatible = "mediatek,mt8195-vdo1-rdma";
2937 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2939 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xa000 0x1000>;
2943 compatible = "mediatek,mt8195-vdo1-rdma";
2947 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2949 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xb000 0x1000>;
2952 merge1: vpp-merge@1c10c000 {
2953 compatible = "mediatek,mt8195-disp-merge";
2958 clock-names = "merge","merge_async";
2959 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2960 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xc000 0x1000>;
2961 mediatek,merge-mute;
2965 merge2: vpp-merge@1c10d000 {
2966 compatible = "mediatek,mt8195-disp-merge";
2971 clock-names = "merge","merge_async";
2972 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2973 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xd000 0x1000>;
2974 mediatek,merge-mute;
2978 merge3: vpp-merge@1c10e000 {
2979 compatible = "mediatek,mt8195-disp-merge";
2984 clock-names = "merge","merge_async";
2985 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2986 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xe000 0x1000>;
2987 mediatek,merge-mute;
2991 merge4: vpp-merge@1c10f000 {
2992 compatible = "mediatek,mt8195-disp-merge";
2997 clock-names = "merge","merge_async";
2998 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
2999 mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0xf000 0x1000>;
3000 mediatek,merge-mute;
3004 merge5: vpp-merge@1c110000 {
3005 compatible = "mediatek,mt8195-disp-merge";
3010 clock-names = "merge","merge_async";
3011 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3012 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x0000 0x1000>;
3013 mediatek,merge-fifo-en;
3017 dp_intf1: dp-intf@1c113000 {
3018 compatible = "mediatek,mt8195-dp-intf";
3021 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3025 clock-names = "engine", "pixel", "pll";
3029 ethdr0: hdr-engine@1c114000 {
3030 compatible = "mediatek,mt8195-disp-ethdr";
3038 reg-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3040 mediatek,gce-client-reg = <&gce0 SUBSYS_1c11XXXX 0x4000 0x1000>,
3060 clock-names = "mixer", "vdo_fe0", "vdo_fe1", "gfx_fe0", "gfx_fe1",
3064 power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
3073 reset-names = "vdo_fe0_async", "vdo_fe1_async", "gfx_fe0_async",
3077 edp_tx: edp-tx@1c500000 {
3078 compatible = "mediatek,mt8195-edp-tx";
3080 nvmem-cells = <&dp_calibration>;
3081 nvmem-cell-names = "dp_calibration_data";
3082 power-domains = <&spm MT8195_POWER_DOMAIN_EPD_TX>;
3084 max-linkrate-mhz = <8100>;
3088 dp_tx: dp-tx@1c600000 {
3089 compatible = "mediatek,mt8195-dp-tx";
3091 nvmem-cells = <&dp_calibration>;
3092 nvmem-cell-names = "dp_calibration_data";
3093 power-domains = <&spm MT8195_POWER_DOMAIN_DP_TX>;
3095 max-linkrate-mhz = <8100>;
3100 thermal_zones: thermal-zones {
3101 cpu0-thermal {
3102 polling-delay = <1000>;
3103 polling-delay-passive = <250>;
3104 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>;
3107 cpu0_alert: trip-alert {
3113 cpu0_crit: trip-crit {
3120 cooling-maps {
3123 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3131 cpu1-thermal {
3132 polling-delay = <1000>;
3133 polling-delay-passive = <250>;
3134 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU1>;
3137 cpu1_alert: trip-alert {
3143 cpu1_crit: trip-crit {
3150 cooling-maps {
3153 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3161 cpu2-thermal {
3162 polling-delay = <1000>;
3163 polling-delay-passive = <250>;
3164 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU2>;
3167 cpu2_alert: trip-alert {
3173 cpu2_crit: trip-crit {
3180 cooling-maps {
3183 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3191 cpu3-thermal {
3192 polling-delay = <1000>;
3193 polling-delay-passive = <250>;
3194 thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU3>;
3197 cpu3_alert: trip-alert {
3203 cpu3_crit: trip-crit {
3210 cooling-maps {
3213 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3221 cpu4-thermal {
3222 polling-delay = <1000>;
3223 polling-delay-passive = <250>;
3224 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU0>;
3227 cpu4_alert: trip-alert {
3233 cpu4_crit: trip-crit {
3240 cooling-maps {
3243 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3251 cpu5-thermal {
3252 polling-delay = <1000>;
3253 polling-delay-passive = <250>;
3254 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU1>;
3257 cpu5_alert: trip-alert {
3263 cpu5_crit: trip-crit {
3270 cooling-maps {
3273 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3281 cpu6-thermal {
3282 polling-delay = <1000>;
3283 polling-delay-passive = <250>;
3284 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU2>;
3287 cpu6_alert: trip-alert {
3293 cpu6_crit: trip-crit {
3300 cooling-maps {
3303 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3311 cpu7-thermal {
3312 polling-delay = <1000>;
3313 polling-delay-passive = <250>;
3314 thermal-sensors = <&lvts_mcu MT8195_MCU_BIG_CPU3>;
3317 cpu7_alert: trip-alert {
3323 cpu7_crit: trip-crit {
3330 cooling-maps {
3333 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3341 vpu0-thermal {
3342 polling-delay = <1000>;
3343 polling-delay-passive = <250>;
3344 thermal-sensors = <&lvts_ap MT8195_AP_VPU0>;
3347 vpu0_alert: trip-alert {
3353 vpu0_crit: trip-crit {
3361 vpu1-thermal {
3362 polling-delay = <1000>;
3363 polling-delay-passive = <250>;
3364 thermal-sensors = <&lvts_ap MT8195_AP_VPU1>;
3367 vpu1_alert: trip-alert {
3373 vpu1_crit: trip-crit {
3381 gpu0-thermal {
3382 polling-delay = <1000>;
3383 polling-delay-passive = <250>;
3384 thermal-sensors = <&lvts_ap MT8195_AP_GPU0>;
3387 gpu0_alert: trip-alert {
3393 gpu0_crit: trip-crit {
3401 gpu1-thermal {
3402 polling-delay = <1000>;
3403 polling-delay-passive = <250>;
3404 thermal-sensors = <&lvts_ap MT8195_AP_GPU1>;
3407 gpu1_alert: trip-alert {
3413 gpu1_crit: trip-crit {
3421 vdec-thermal {
3422 polling-delay = <1000>;
3423 polling-delay-passive = <250>;
3424 thermal-sensors = <&lvts_ap MT8195_AP_VDEC>;
3427 vdec_alert: trip-alert {
3433 vdec_crit: trip-crit {
3441 img-thermal {
3442 polling-delay = <1000>;
3443 polling-delay-passive = <250>;
3444 thermal-sensors = <&lvts_ap MT8195_AP_IMG>;
3447 img_alert: trip-alert {
3453 img_crit: trip-crit {
3461 infra-thermal {
3462 polling-delay = <1000>;
3463 polling-delay-passive = <250>;
3464 thermal-sensors = <&lvts_ap MT8195_AP_INFRA>;
3467 infra_alert: trip-alert {
3473 infra_crit: trip-crit {
3481 cam0-thermal {
3482 polling-delay = <1000>;
3483 polling-delay-passive = <250>;
3484 thermal-sensors = <&lvts_ap MT8195_AP_CAM0>;
3487 cam0_alert: trip-alert {
3493 cam0_crit: trip-crit {
3501 cam1-thermal {
3502 polling-delay = <1000>;
3503 polling-delay-passive = <250>;
3504 thermal-sensors = <&lvts_ap MT8195_AP_CAM1>;
3507 cam1_alert: trip-alert {
3513 cam1_crit: trip-crit {