Lines Matching +full:mt8195 +full:- +full:vencsys
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 * Author: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
6 /dts-v1/;
7 #include <dt-bindings/clock/mt8186-clk.h>
8 #include <dt-bindings/gce/mt8186-gce.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/memory/mt8186-memory-port.h>
12 #include <dt-bindings/pinctrl/mt8186-pinfunc.h>
13 #include <dt-bindings/power/mt8186-power.h>
14 #include <dt-bindings/phy/phy.h>
15 #include <dt-bindings/reset/mt8186-resets.h>
19 interrupt-parent = <&gic>;
20 #address-cells = <2>;
21 #size-cells = <2>;
31 compatible = "mediatek,mt8186-cci";
34 clock-names = "cci", "intermediate";
35 operating-points-v2 = <&cci_opp>;
38 cci_opp: opp-table-cci {
39 compatible = "operating-points-v2";
40 opp-shared;
42 cci_opp_0: opp-500000000 {
43 opp-hz = /bits/ 64 <500000000>;
44 opp-microvolt = <600000>;
47 cci_opp_1: opp-560000000 {
48 opp-hz = /bits/ 64 <560000000>;
49 opp-microvolt = <675000>;
52 cci_opp_2: opp-612000000 {
53 opp-hz = /bits/ 64 <612000000>;
54 opp-microvolt = <693750>;
57 cci_opp_3: opp-682000000 {
58 opp-hz = /bits/ 64 <682000000>;
59 opp-microvolt = <718750>;
62 cci_opp_4: opp-752000000 {
63 opp-hz = /bits/ 64 <752000000>;
64 opp-microvolt = <743750>;
67 cci_opp_5: opp-822000000 {
68 opp-hz = /bits/ 64 <822000000>;
69 opp-microvolt = <768750>;
72 cci_opp_6: opp-875000000 {
73 opp-hz = /bits/ 64 <875000000>;
74 opp-microvolt = <781250>;
77 cci_opp_7: opp-927000000 {
78 opp-hz = /bits/ 64 <927000000>;
79 opp-microvolt = <800000>;
82 cci_opp_8: opp-980000000 {
83 opp-hz = /bits/ 64 <980000000>;
84 opp-microvolt = <818750>;
87 cci_opp_9: opp-1050000000 {
88 opp-hz = /bits/ 64 <1050000000>;
89 opp-microvolt = <843750>;
92 cci_opp_10: opp-1120000000 {
93 opp-hz = /bits/ 64 <1120000000>;
94 opp-microvolt = <862500>;
97 cci_opp_11: opp-1155000000 {
98 opp-hz = /bits/ 64 <1155000000>;
99 opp-microvolt = <887500>;
102 cci_opp_12: opp-1190000000 {
103 opp-hz = /bits/ 64 <1190000000>;
104 opp-microvolt = <906250>;
107 cci_opp_13: opp-1260000000 {
108 opp-hz = /bits/ 64 <1260000000>;
109 opp-microvolt = <950000>;
112 cci_opp_14: opp-1330000000 {
113 opp-hz = /bits/ 64 <1330000000>;
114 opp-microvolt = <993750>;
117 cci_opp_15: opp-1400000000 {
118 opp-hz = /bits/ 64 <1400000000>;
119 opp-microvolt = <1031250>;
123 cluster0_opp: opp-table-cluster0 {
124 compatible = "operating-points-v2";
125 opp-shared;
127 opp-500000000 {
128 opp-hz = /bits/ 64 <500000000>;
129 opp-microvolt = <600000>;
130 required-opps = <&cci_opp_0>;
133 opp-774000000 {
134 opp-hz = /bits/ 64 <774000000>;
135 opp-microvolt = <675000>;
136 required-opps = <&cci_opp_1>;
139 opp-875000000 {
140 opp-hz = /bits/ 64 <875000000>;
141 opp-microvolt = <700000>;
142 required-opps = <&cci_opp_2>;
145 opp-975000000 {
146 opp-hz = /bits/ 64 <975000000>;
147 opp-microvolt = <725000>;
148 required-opps = <&cci_opp_3>;
151 opp-1075000000 {
152 opp-hz = /bits/ 64 <1075000000>;
153 opp-microvolt = <750000>;
154 required-opps = <&cci_opp_4>;
157 opp-1175000000 {
158 opp-hz = /bits/ 64 <1175000000>;
159 opp-microvolt = <775000>;
160 required-opps = <&cci_opp_5>;
163 opp-1275000000 {
164 opp-hz = /bits/ 64 <1275000000>;
165 opp-microvolt = <800000>;
166 required-opps = <&cci_opp_6>;
169 opp-1375000000 {
170 opp-hz = /bits/ 64 <1375000000>;
171 opp-microvolt = <825000>;
172 required-opps = <&cci_opp_7>;
175 opp-1500000000 {
176 opp-hz = /bits/ 64 <1500000000>;
177 opp-microvolt = <856250>;
178 required-opps = <&cci_opp_8>;
181 opp-1618000000 {
182 opp-hz = /bits/ 64 <1618000000>;
183 opp-microvolt = <875000>;
184 required-opps = <&cci_opp_9>;
187 opp-1666000000 {
188 opp-hz = /bits/ 64 <1666000000>;
189 opp-microvolt = <900000>;
190 required-opps = <&cci_opp_10>;
193 opp-1733000000 {
194 opp-hz = /bits/ 64 <1733000000>;
195 opp-microvolt = <925000>;
196 required-opps = <&cci_opp_11>;
199 opp-1800000000 {
200 opp-hz = /bits/ 64 <1800000000>;
201 opp-microvolt = <950000>;
202 required-opps = <&cci_opp_12>;
205 opp-1866000000 {
206 opp-hz = /bits/ 64 <1866000000>;
207 opp-microvolt = <981250>;
208 required-opps = <&cci_opp_13>;
211 opp-1933000000 {
212 opp-hz = /bits/ 64 <1933000000>;
213 opp-microvolt = <1006250>;
214 required-opps = <&cci_opp_14>;
217 opp-2000000000 {
218 opp-hz = /bits/ 64 <2000000000>;
219 opp-microvolt = <1031250>;
220 required-opps = <&cci_opp_15>;
224 cluster1_opp: opp-table-cluster1 {
225 compatible = "operating-points-v2";
226 opp-shared;
228 opp-774000000 {
229 opp-hz = /bits/ 64 <774000000>;
230 opp-microvolt = <675000>;
231 required-opps = <&cci_opp_0>;
234 opp-835000000 {
235 opp-hz = /bits/ 64 <835000000>;
236 opp-microvolt = <693750>;
237 required-opps = <&cci_opp_1>;
240 opp-919000000 {
241 opp-hz = /bits/ 64 <919000000>;
242 opp-microvolt = <718750>;
243 required-opps = <&cci_opp_2>;
246 opp-1002000000 {
247 opp-hz = /bits/ 64 <1002000000>;
248 opp-microvolt = <743750>;
249 required-opps = <&cci_opp_3>;
252 opp-1085000000 {
253 opp-hz = /bits/ 64 <1085000000>;
254 opp-microvolt = <775000>;
255 required-opps = <&cci_opp_4>;
258 opp-1169000000 {
259 opp-hz = /bits/ 64 <1169000000>;
260 opp-microvolt = <800000>;
261 required-opps = <&cci_opp_5>;
264 opp-1308000000 {
265 opp-hz = /bits/ 64 <1308000000>;
266 opp-microvolt = <843750>;
267 required-opps = <&cci_opp_6>;
270 opp-1419000000 {
271 opp-hz = /bits/ 64 <1419000000>;
272 opp-microvolt = <875000>;
273 required-opps = <&cci_opp_7>;
276 opp-1530000000 {
277 opp-hz = /bits/ 64 <1530000000>;
278 opp-microvolt = <912500>;
279 required-opps = <&cci_opp_8>;
282 opp-1670000000 {
283 opp-hz = /bits/ 64 <1670000000>;
284 opp-microvolt = <956250>;
285 required-opps = <&cci_opp_9>;
288 opp-1733000000 {
289 opp-hz = /bits/ 64 <1733000000>;
290 opp-microvolt = <981250>;
291 required-opps = <&cci_opp_10>;
294 opp-1796000000 {
295 opp-hz = /bits/ 64 <1796000000>;
296 opp-microvolt = <1012500>;
297 required-opps = <&cci_opp_11>;
300 opp-1860000000 {
301 opp-hz = /bits/ 64 <1860000000>;
302 opp-microvolt = <1037500>;
303 required-opps = <&cci_opp_12>;
306 opp-1923000000 {
307 opp-hz = /bits/ 64 <1923000000>;
308 opp-microvolt = <1062500>;
309 required-opps = <&cci_opp_13>;
312 cluster1_opp_14: opp-1986000000 {
313 opp-hz = /bits/ 64 <1986000000>;
314 opp-microvolt = <1093750>;
315 required-opps = <&cci_opp_14>;
318 cluster1_opp_15: opp-2050000000 {
319 opp-hz = /bits/ 64 <2050000000>;
320 opp-microvolt = <1118750>;
321 required-opps = <&cci_opp_15>;
326 #address-cells = <1>;
327 #size-cells = <0>;
329 cpu-map {
367 compatible = "arm,cortex-a55";
369 enable-method = "psci";
370 clock-frequency = <2000000000>;
373 clock-names = "cpu", "intermediate";
374 operating-points-v2 = <&cluster0_opp>;
375 dynamic-power-coefficient = <84>;
376 capacity-dmips-mhz = <382>;
377 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
378 i-cache-size = <32768>;
379 i-cache-line-size = <64>;
380 i-cache-sets = <128>;
381 d-cache-size = <32768>;
382 d-cache-line-size = <64>;
383 d-cache-sets = <128>;
384 next-level-cache = <&l2_0>;
385 #cooling-cells = <2>;
391 compatible = "arm,cortex-a55";
393 enable-method = "psci";
394 clock-frequency = <2000000000>;
397 clock-names = "cpu", "intermediate";
398 operating-points-v2 = <&cluster0_opp>;
399 dynamic-power-coefficient = <84>;
400 capacity-dmips-mhz = <382>;
401 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
402 i-cache-size = <32768>;
403 i-cache-line-size = <64>;
404 i-cache-sets = <128>;
405 d-cache-size = <32768>;
406 d-cache-line-size = <64>;
407 d-cache-sets = <128>;
408 next-level-cache = <&l2_0>;
409 #cooling-cells = <2>;
415 compatible = "arm,cortex-a55";
417 enable-method = "psci";
418 clock-frequency = <2000000000>;
421 clock-names = "cpu", "intermediate";
422 operating-points-v2 = <&cluster0_opp>;
423 dynamic-power-coefficient = <84>;
424 capacity-dmips-mhz = <382>;
425 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
426 i-cache-size = <32768>;
427 i-cache-line-size = <64>;
428 i-cache-sets = <128>;
429 d-cache-size = <32768>;
430 d-cache-line-size = <64>;
431 d-cache-sets = <128>;
432 next-level-cache = <&l2_0>;
433 #cooling-cells = <2>;
439 compatible = "arm,cortex-a55";
441 enable-method = "psci";
442 clock-frequency = <2000000000>;
445 clock-names = "cpu", "intermediate";
446 operating-points-v2 = <&cluster0_opp>;
447 dynamic-power-coefficient = <84>;
448 capacity-dmips-mhz = <382>;
449 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
450 i-cache-size = <32768>;
451 i-cache-line-size = <64>;
452 i-cache-sets = <128>;
453 d-cache-size = <32768>;
454 d-cache-line-size = <64>;
455 d-cache-sets = <128>;
456 next-level-cache = <&l2_0>;
457 #cooling-cells = <2>;
463 compatible = "arm,cortex-a55";
465 enable-method = "psci";
466 clock-frequency = <2000000000>;
469 clock-names = "cpu", "intermediate";
470 operating-points-v2 = <&cluster0_opp>;
471 dynamic-power-coefficient = <84>;
472 capacity-dmips-mhz = <382>;
473 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
474 i-cache-size = <32768>;
475 i-cache-line-size = <64>;
476 i-cache-sets = <128>;
477 d-cache-size = <32768>;
478 d-cache-line-size = <64>;
479 d-cache-sets = <128>;
480 next-level-cache = <&l2_0>;
481 #cooling-cells = <2>;
487 compatible = "arm,cortex-a55";
489 enable-method = "psci";
490 clock-frequency = <2000000000>;
493 clock-names = "cpu", "intermediate";
494 operating-points-v2 = <&cluster0_opp>;
495 dynamic-power-coefficient = <84>;
496 capacity-dmips-mhz = <382>;
497 cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
498 i-cache-size = <32768>;
499 i-cache-line-size = <64>;
500 i-cache-sets = <128>;
501 d-cache-size = <32768>;
502 d-cache-line-size = <64>;
503 d-cache-sets = <128>;
504 next-level-cache = <&l2_0>;
505 #cooling-cells = <2>;
511 compatible = "arm,cortex-a76";
513 enable-method = "psci";
514 clock-frequency = <2050000000>;
517 clock-names = "cpu", "intermediate";
518 operating-points-v2 = <&cluster1_opp>;
519 dynamic-power-coefficient = <335>;
520 capacity-dmips-mhz = <1024>;
521 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
522 i-cache-size = <65536>;
523 i-cache-line-size = <64>;
524 i-cache-sets = <256>;
525 d-cache-size = <65536>;
526 d-cache-line-size = <64>;
527 d-cache-sets = <256>;
528 next-level-cache = <&l2_1>;
529 #cooling-cells = <2>;
535 compatible = "arm,cortex-a76";
537 enable-method = "psci";
538 clock-frequency = <2050000000>;
541 clock-names = "cpu", "intermediate";
542 operating-points-v2 = <&cluster1_opp>;
543 dynamic-power-coefficient = <335>;
544 capacity-dmips-mhz = <1024>;
545 cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
546 i-cache-size = <65536>;
547 i-cache-line-size = <64>;
548 i-cache-sets = <256>;
549 d-cache-size = <65536>;
550 d-cache-line-size = <64>;
551 d-cache-sets = <256>;
552 next-level-cache = <&l2_1>;
553 #cooling-cells = <2>;
557 idle-states {
558 entry-method = "psci";
560 cpu_ret_l: cpu-retention-l {
561 compatible = "arm,idle-state";
562 arm,psci-suspend-param = <0x00010001>;
563 local-timer-stop;
564 entry-latency-us = <50>;
565 exit-latency-us = <100>;
566 min-residency-us = <1600>;
569 cpu_ret_b: cpu-retention-b {
570 compatible = "arm,idle-state";
571 arm,psci-suspend-param = <0x00010001>;
572 local-timer-stop;
573 entry-latency-us = <50>;
574 exit-latency-us = <100>;
575 min-residency-us = <1400>;
578 cpu_off_l: cpu-off-l {
579 compatible = "arm,idle-state";
580 arm,psci-suspend-param = <0x01010001>;
581 local-timer-stop;
582 entry-latency-us = <100>;
583 exit-latency-us = <250>;
584 min-residency-us = <2100>;
587 cpu_off_b: cpu-off-b {
588 compatible = "arm,idle-state";
589 arm,psci-suspend-param = <0x01010001>;
590 local-timer-stop;
591 entry-latency-us = <100>;
592 exit-latency-us = <250>;
593 min-residency-us = <1900>;
597 l2_0: l2-cache0 {
599 cache-level = <2>;
600 cache-size = <131072>;
601 cache-line-size = <64>;
602 cache-sets = <512>;
603 next-level-cache = <&l3_0>;
604 cache-unified;
607 l2_1: l2-cache1 {
609 cache-level = <2>;
610 cache-size = <262144>;
611 cache-line-size = <64>;
612 cache-sets = <512>;
613 next-level-cache = <&l3_0>;
614 cache-unified;
617 l3_0: l3-cache {
619 cache-level = <3>;
620 cache-size = <1048576>;
621 cache-line-size = <64>;
622 cache-sets = <1024>;
623 cache-unified;
627 clk13m: fixed-factor-clock-13m {
628 compatible = "fixed-factor-clock";
629 #clock-cells = <0>;
631 clock-div = <2>;
632 clock-mult = <1>;
633 clock-output-names = "clk13m";
636 clk26m: oscillator-26m {
637 compatible = "fixed-clock";
638 #clock-cells = <0>;
639 clock-frequency = <26000000>;
640 clock-output-names = "clk26m";
643 clk32k: oscillator-32k {
644 compatible = "fixed-clock";
645 #clock-cells = <0>;
646 clock-frequency = <32768>;
647 clock-output-names = "clk32k";
650 gpu_opp_table: opp-table-gpu {
651 compatible = "operating-points-v2";
653 opp-299000000 {
654 opp-hz = /bits/ 64 <299000000>;
655 opp-microvolt = <612500>;
656 opp-supported-hw = <0xff>;
659 opp-332000000 {
660 opp-hz = /bits/ 64 <332000000>;
661 opp-microvolt = <625000>;
662 opp-supported-hw = <0xff>;
665 opp-366000000 {
666 opp-hz = /bits/ 64 <366000000>;
667 opp-microvolt = <637500>;
668 opp-supported-hw = <0xff>;
671 opp-400000000 {
672 opp-hz = /bits/ 64 <400000000>;
673 opp-microvolt = <643750>;
674 opp-supported-hw = <0xff>;
677 opp-434000000 {
678 opp-hz = /bits/ 64 <434000000>;
679 opp-microvolt = <656250>;
680 opp-supported-hw = <0xff>;
683 opp-484000000 {
684 opp-hz = /bits/ 64 <484000000>;
685 opp-microvolt = <668750>;
686 opp-supported-hw = <0xff>;
689 opp-535000000 {
690 opp-hz = /bits/ 64 <535000000>;
691 opp-microvolt = <687500>;
692 opp-supported-hw = <0xff>;
695 opp-586000000 {
696 opp-hz = /bits/ 64 <586000000>;
697 opp-microvolt = <700000>;
698 opp-supported-hw = <0xff>;
701 opp-637000000 {
702 opp-hz = /bits/ 64 <637000000>;
703 opp-microvolt = <712500>;
704 opp-supported-hw = <0xff>;
707 opp-690000000 {
708 opp-hz = /bits/ 64 <690000000>;
709 opp-microvolt = <737500>;
710 opp-supported-hw = <0xff>;
713 opp-743000000 {
714 opp-hz = /bits/ 64 <743000000>;
715 opp-microvolt = <756250>;
716 opp-supported-hw = <0xff>;
719 opp-796000000 {
720 opp-hz = /bits/ 64 <796000000>;
721 opp-microvolt = <781250>;
722 opp-supported-hw = <0xff>;
725 opp-850000000 {
726 opp-hz = /bits/ 64 <850000000>;
727 opp-microvolt = <800000>;
728 opp-supported-hw = <0xff>;
731 opp-900000000-3 {
732 opp-hz = /bits/ 64 <900000000>;
733 opp-microvolt = <850000>;
734 opp-supported-hw = <0x8>;
737 opp-900000000-4 {
738 opp-hz = /bits/ 64 <900000000>;
739 opp-microvolt = <837500>;
740 opp-supported-hw = <0x10>;
743 opp-900000000-5 {
744 opp-hz = /bits/ 64 <900000000>;
745 opp-microvolt = <825000>;
746 opp-supported-hw = <0x30>;
749 opp-950000000-3 {
750 opp-hz = /bits/ 64 <950000000>;
751 opp-microvolt = <900000>;
752 opp-supported-hw = <0x8>;
755 opp-950000000-4 {
756 opp-hz = /bits/ 64 <950000000>;
757 opp-microvolt = <875000>;
758 opp-supported-hw = <0x10>;
761 opp-950000000-5 {
762 opp-hz = /bits/ 64 <950000000>;
763 opp-microvolt = <850000>;
764 opp-supported-hw = <0x30>;
767 opp-1000000000-3 {
768 opp-hz = /bits/ 64 <1000000000>;
769 opp-microvolt = <950000>;
770 opp-supported-hw = <0x8>;
773 opp-1000000000-4 {
774 opp-hz = /bits/ 64 <1000000000>;
775 opp-microvolt = <912500>;
776 opp-supported-hw = <0x10>;
779 opp-1000000000-5 {
780 opp-hz = /bits/ 64 <1000000000>;
781 opp-microvolt = <875000>;
782 opp-supported-hw = <0x30>;
786 pmu-a55 {
787 compatible = "arm,cortex-a55-pmu";
788 interrupt-parent = <&gic>;
792 pmu-a76 {
793 compatible = "arm,cortex-a76-pmu";
794 interrupt-parent = <&gic>;
799 compatible = "arm,psci-1.0";
804 compatible = "arm,armv8-timer";
805 interrupt-parent = <&gic>;
813 #address-cells = <2>;
814 #size-cells = <2>;
815 compatible = "simple-bus";
816 dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
819 gic: interrupt-controller@c000000 {
820 compatible = "arm,gic-v3";
821 #interrupt-cells = <4>;
822 #redistributor-regions = <1>;
823 interrupt-parent = <&gic>;
824 interrupt-controller;
829 ppi-partitions {
830 ppi_cluster0: interrupt-partition-0 {
834 ppi_cluster1: interrupt-partition-1 {
841 compatible = "mediatek,mt8186-mcusys", "syscon";
843 #clock-cells = <1>;
847 compatible = "mediatek,mt8186-topckgen", "syscon";
849 #clock-cells = <1>;
853 compatible = "mediatek,mt8186-infracfg_ao", "syscon";
855 #clock-cells = <1>;
856 #reset-cells = <1>;
860 compatible = "mediatek,mt8186-pericfg", "syscon";
865 compatible = "mediatek,mt8186-pinctrl";
874 reg-names = "iocfg0", "iocfg_lt", "iocfg_lm", "iocfg_lb",
876 gpio-controller;
877 #gpio-cells = <2>;
878 gpio-ranges = <&pio 0 0 185>;
879 interrupt-controller;
881 #interrupt-cells = <2>;
885 compatible = "mediatek,mt8186-scpsys", "syscon", "simple-mfd";
889 spm: power-controller {
890 compatible = "mediatek,mt8186-power-controller";
891 #address-cells = <1>;
892 #size-cells = <0>;
893 #power-domain-cells = <1>;
896 mfg0: power-domain@MT8186_POWER_DOMAIN_MFG0 {
899 clock-names = "mfg00";
900 #address-cells = <1>;
901 #size-cells = <0>;
902 #power-domain-cells = <1>;
904 mfg1: power-domain@MT8186_POWER_DOMAIN_MFG1 {
907 #address-cells = <1>;
908 #size-cells = <0>;
909 #power-domain-cells = <1>;
911 power-domain@MT8186_POWER_DOMAIN_MFG2 {
913 #power-domain-cells = <0>;
916 power-domain@MT8186_POWER_DOMAIN_MFG3 {
918 #power-domain-cells = <0>;
923 power-domain@MT8186_POWER_DOMAIN_CSIRX_TOP {
927 clock-names = "csirx_top0", "csirx_top1";
928 #power-domain-cells = <0>;
931 power-domain@MT8186_POWER_DOMAIN_SSUSB {
933 #power-domain-cells = <0>;
936 power-domain@MT8186_POWER_DOMAIN_SSUSB_P1 {
938 #power-domain-cells = <0>;
941 power-domain@MT8186_POWER_DOMAIN_ADSP_AO {
945 clock-names = "audioadsp", "adsp_bus";
946 #address-cells = <1>;
947 #size-cells = <0>;
948 #power-domain-cells = <1>;
950 power-domain@MT8186_POWER_DOMAIN_ADSP_INFRA {
952 #address-cells = <1>;
953 #size-cells = <0>;
954 #power-domain-cells = <1>;
956 power-domain@MT8186_POWER_DOMAIN_ADSP_TOP {
959 #power-domain-cells = <0>;
964 power-domain@MT8186_POWER_DOMAIN_CONN_ON {
967 #power-domain-cells = <0>;
970 power-domain@MT8186_POWER_DOMAIN_DIS {
978 clock-names = "disp", "mdp", "smi_infra", "smi_common",
981 #address-cells = <1>;
982 #size-cells = <0>;
983 #power-domain-cells = <1>;
985 power-domain@MT8186_POWER_DOMAIN_VDEC {
989 clock-names = "vdec0", "larb";
991 #power-domain-cells = <0>;
994 power-domain@MT8186_POWER_DOMAIN_CAM {
1003 clock-names = "cam-top", "cam0", "cam1", "cam2",
1004 "cam3", "cam-tm", "gals";
1006 #address-cells = <1>;
1007 #size-cells = <0>;
1008 #power-domain-cells = <1>;
1010 power-domain@MT8186_POWER_DOMAIN_CAM_RAWB {
1012 #power-domain-cells = <0>;
1015 power-domain@MT8186_POWER_DOMAIN_CAM_RAWA {
1017 #power-domain-cells = <0>;
1021 power-domain@MT8186_POWER_DOMAIN_IMG {
1025 clock-names = "img-top", "gals";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029 #power-domain-cells = <1>;
1031 power-domain@MT8186_POWER_DOMAIN_IMG2 {
1033 #power-domain-cells = <0>;
1037 power-domain@MT8186_POWER_DOMAIN_IPE {
1044 clock-names = "ipe-top", "ipe-larb0", "ipe-larb1",
1045 "ipe-smi", "ipe-gals";
1047 #power-domain-cells = <0>;
1050 power-domain@MT8186_POWER_DOMAIN_VENC {
1053 <&vencsys CLK_VENC_CKE1_VENC>;
1054 clock-names = "venc0", "larb";
1056 #power-domain-cells = <0>;
1059 power-domain@MT8186_POWER_DOMAIN_WPE {
1064 clock-names = "wpe0", "larb-ck", "larb-pclk";
1066 #power-domain-cells = <0>;
1073 compatible = "mediatek,mt8186-wdt";
1074 mediatek,disable-extrst;
1076 #reset-cells = <1>;
1080 compatible = "mediatek,mt8186-apmixedsys", "syscon";
1082 #clock-cells = <1>;
1086 compatible = "mediatek,mt8186-pwrap", "syscon";
1088 reg-names = "pwrap";
1092 clock-names = "spi", "wrap";
1096 compatible = "mediatek,mt8186-spmi", "mediatek,mt8195-spmi";
1098 reg-names = "pmif", "spmimst";
1102 clock-names = "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux";
1103 assigned-clocks = <&topckgen CLK_TOP_SPMI_MST>;
1104 assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
1111 compatible = "mediatek,mt8186-timer",
1112 "mediatek,mt6765-timer";
1119 compatible = "mediatek,mt8186-gce";
1122 clock-names = "gce";
1124 #mbox-cells = <2>;
1128 compatible = "mediatek,mt8186-scp";
1131 reg-names = "sram", "cfg";
1136 compatible = "mediatek,mt8186-dsp";
1139 reg-names = "cfg", "sram", "sec", "bus";
1141 clock-names = "audiodsp", "adsp_bus";
1142 assigned-clocks = <&topckgen CLK_TOP_AUDIODSP>,
1144 assigned-clock-parents = <&clk26m>, <&topckgen CLK_TOP_MAINPLL_D2_D2>;
1145 mbox-names = "rx", "tx";
1147 power-domains = <&spm MT8186_POWER_DOMAIN_ADSP_TOP>;
1152 compatible = "mediatek,mt8186-adsp-mbox";
1153 #mbox-cells = <0>;
1159 compatible = "mediatek,mt8186-adsp-mbox";
1160 #mbox-cells = <0>;
1166 compatible = "mediatek,mt8186-nor";
1172 clock-names = "spi", "sf", "axi", "axi_s";
1173 assigned-clocks = <&topckgen CLK_TOP_SPINOR>;
1174 assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D3_D8>;
1180 compatible = "mediatek,mt8186-auxadc", "mediatek,mt8173-auxadc";
1182 #io-channel-cells = <1>;
1184 clock-names = "main";
1188 compatible = "mediatek,mt8186-uart",
1189 "mediatek,mt6577-uart";
1193 clock-names = "baud", "bus";
1198 compatible = "mediatek,mt8186-uart",
1199 "mediatek,mt6577-uart";
1203 clock-names = "baud", "bus";
1208 compatible = "mediatek,mt8186-i2c";
1214 clock-names = "main", "dma";
1215 clock-div = <1>;
1216 #address-cells = <1>;
1217 #size-cells = <0>;
1222 compatible = "mediatek,mt8186-i2c";
1228 clock-names = "main", "dma";
1229 clock-div = <1>;
1230 #address-cells = <1>;
1231 #size-cells = <0>;
1236 compatible = "mediatek,mt8186-i2c";
1242 clock-names = "main", "dma";
1243 clock-div = <1>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1250 compatible = "mediatek,mt8186-i2c";
1256 clock-names = "main", "dma";
1257 clock-div = <1>;
1258 #address-cells = <1>;
1259 #size-cells = <0>;
1264 compatible = "mediatek,mt8186-i2c";
1270 clock-names = "main", "dma";
1271 clock-div = <1>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1278 compatible = "mediatek,mt8186-i2c";
1284 clock-names = "main", "dma";
1285 clock-div = <1>;
1286 #address-cells = <1>;
1287 #size-cells = <0>;
1292 compatible = "mediatek,mt8186-i2c";
1298 clock-names = "main", "dma";
1299 clock-div = <1>;
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1306 compatible = "mediatek,mt8186-i2c";
1312 clock-names = "main", "dma";
1313 clock-div = <1>;
1314 #address-cells = <1>;
1315 #size-cells = <0>;
1320 compatible = "mediatek,mt8186-i2c";
1326 clock-names = "main", "dma";
1327 clock-div = <1>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1334 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1335 #address-cells = <1>;
1336 #size-cells = <0>;
1342 clock-names = "parent-clk", "sel-clk", "spi-clk";
1347 compatible = "mediatek,mt8186-disp-pwm", "mediatek,mt8183-disp-pwm";
1350 #pwm-cells = <2>;
1353 clock-names = "main", "mm";
1358 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1359 #address-cells = <1>;
1360 #size-cells = <0>;
1366 clock-names = "parent-clk", "sel-clk", "spi-clk";
1371 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1372 #address-cells = <1>;
1373 #size-cells = <0>;
1379 clock-names = "parent-clk", "sel-clk", "spi-clk";
1384 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1385 #address-cells = <1>;
1386 #size-cells = <0>;
1392 clock-names = "parent-clk", "sel-clk", "spi-clk";
1397 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1398 #address-cells = <1>;
1399 #size-cells = <0>;
1405 clock-names = "parent-clk", "sel-clk", "spi-clk";
1410 compatible = "mediatek,mt8186-spi", "mediatek,mt6765-spi";
1411 #address-cells = <1>;
1412 #size-cells = <0>;
1418 clock-names = "parent-clk", "sel-clk", "spi-clk";
1422 imp_iic_wrap: clock-controller@11017000 {
1423 compatible = "mediatek,mt8186-imp_iic_wrap";
1425 #clock-cells = <1>;
1429 compatible = "mediatek,mt8186-uart",
1430 "mediatek,mt6577-uart";
1434 clock-names = "baud", "bus";
1439 compatible = "mediatek,mt8186-i2c";
1445 clock-names = "main", "dma";
1446 clock-div = <1>;
1447 #address-cells = <1>;
1448 #size-cells = <0>;
1452 afe: audio-controller@11210000 {
1453 compatible = "mediatek,mt8186-sound";
1480 clock-names = "aud_infra_clk",
1510 reset-names = "audiosys";
1515 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1517 reg-names = "mac", "ippc";
1522 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1525 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB>;
1526 #address-cells = <2>;
1527 #size-cells = <2>;
1532 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1534 reg-names = "mac";
1540 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck";
1542 mediatek,syscon-wakeup = <&pericfg 0x420 2>;
1543 wakeup-source;
1549 compatible = "mediatek,mt8186-mmc",
1550 "mediatek,mt8183-mmc";
1557 clock-names = "source", "hclk", "source_cg", "crypto";
1559 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0>;
1560 assigned-clock-parents = <&apmixedsys CLK_APMIXED_MSDCPLL>;
1565 compatible = "mediatek,mt8186-mmc",
1566 "mediatek,mt8183-mmc";
1572 clock-names = "source", "hclk", "source_cg";
1574 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
1575 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
1580 compatible = "mediatek,mt8186-mtu3", "mediatek,mtu3";
1582 reg-names = "mac", "ippc";
1587 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
1590 power-domains = <&spm MT8186_POWER_DOMAIN_SSUSB_P1>;
1591 #address-cells = <2>;
1592 #size-cells = <2>;
1597 compatible = "mediatek,mt8186-xhci", "mediatek,mtk-xhci";
1599 reg-names = "mac";
1605 clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck","xhci_ck";
1607 mediatek,syscon-wakeup = <&pericfg 0x424 2>;
1608 wakeup-source;
1613 u3phy0: t-phy@11c80000 {
1614 compatible = "mediatek,mt8186-tphy",
1615 "mediatek,generic-tphy-v2";
1616 #address-cells = <1>;
1617 #size-cells = <1>;
1621 u2port1: usb-phy@0 {
1624 clock-names = "ref";
1625 #phy-cells = <1>;
1628 u3port1: usb-phy@700 {
1631 clock-names = "ref";
1632 #phy-cells = <1>;
1636 u3phy1: t-phy@11ca0000 {
1637 compatible = "mediatek,mt8186-tphy",
1638 "mediatek,generic-tphy-v2";
1639 #address-cells = <1>;
1640 #size-cells = <1>;
1644 u2port0: usb-phy@0 {
1647 clock-names = "ref";
1648 #phy-cells = <1>;
1654 compatible = "mediatek,mt8186-efuse", "mediatek,efuse";
1656 #address-cells = <1>;
1657 #size-cells = <1>;
1659 gpu_speedbin: gpu-speed-bin@59c {
1665 mipi_tx0: dsi-phy@11cc0000 {
1666 compatible = "mediatek,mt8183-mipi-tx";
1669 #clock-cells = <0>;
1670 #phy-cells = <0>;
1671 clock-output-names = "mipi_tx0_pll";
1675 mfgsys: clock-controller@13000000 {
1676 compatible = "mediatek,mt8186-mfgsys";
1678 #clock-cells = <1>;
1682 compatible = "mediatek,mt8186-mali",
1683 "arm,mali-bifrost";
1690 interrupt-names = "job", "mmu", "gpu";
1691 power-domains = <&spm MT8186_POWER_DOMAIN_MFG2>,
1693 power-domain-names = "core0", "core1";
1694 #cooling-cells = <2>;
1695 nvmem-cells = <&gpu_speedbin>;
1696 nvmem-cell-names = "speed-bin";
1697 operating-points-v2 = <&gpu_opp_table>;
1698 dynamic-power-coefficient = <4687>;
1703 compatible = "mediatek,mt8186-mmsys", "syscon";
1705 #clock-cells = <1>;
1706 #reset-cells = <1>;
1709 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
1713 compatible = "mediatek,mt8186-disp-mutex";
1717 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
1718 mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
1720 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1724 compatible = "mediatek,mt8186-smi-common";
1728 clock-names = "apb", "smi", "gals0", "gals1";
1729 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1733 compatible = "mediatek,mt8186-smi-larb";
1737 clock-names = "apb", "smi";
1738 mediatek,larb-id = <0>;
1740 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1744 compatible = "mediatek,mt8186-smi-larb";
1748 clock-names = "apb", "smi";
1749 mediatek,larb-id = <1>;
1751 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1755 compatible = "mediatek,mt8186-disp-ovl", "mediatek,mt8192-disp-ovl";
1760 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
1761 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1765 compatible = "mediatek,mt8186-disp-ovl-2l", "mediatek,mt8192-disp-ovl-2l";
1770 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
1771 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1775 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1780 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x7000 0x1000>;
1781 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1785 compatible = "mediatek,mt8186-disp-color", "mediatek,mt8173-disp-color";
1789 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x8000 0x1000>;
1790 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1794 compatible = "mediatek,mt8186-dpi";
1799 clock-names = "pixel", "engine", "pll";
1800 assigned-clocks = <&topckgen CLK_TOP_DPI>;
1801 assigned-clock-parents = <&topckgen CLK_TOP_TVDPLL_D2>;
1811 compatible = "mediatek,mt8186-disp-ccorr", "mediatek,mt8192-disp-ccorr";
1815 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xb000 0x1000>;
1816 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1820 compatible = "mediatek,mt8186-disp-aal", "mediatek,mt8183-disp-aal";
1824 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xc000 0x1000>;
1825 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1829 compatible = "mediatek,mt8186-disp-gamma", "mediatek,mt8183-disp-gamma";
1833 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xd000 0x1000>;
1834 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1838 compatible = "mediatek,mt8186-disp-postmask",
1839 "mediatek,mt8192-disp-postmask";
1843 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xe000 0x1000>;
1844 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1848 compatible = "mediatek,mt8186-disp-dither", "mediatek,mt8183-disp-dither";
1852 mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0xf000 0x1000>;
1853 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1857 compatible = "mediatek,mt8186-dsi";
1862 clock-names = "engine", "digital", "hs";
1864 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1867 phy-names = "dphy";
1876 compatible = "mediatek,mt8186-iommu-mm";
1879 clock-names = "bclk";
1885 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1886 #iommu-cells = <1>;
1890 compatible = "mediatek,mt8186-disp-rdma", "mediatek,mt8183-disp-rdma";
1895 mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xf000 0x1000>;
1896 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
1899 wpesys: clock-controller@14020000 {
1900 compatible = "mediatek,mt8186-wpesys";
1902 #clock-cells = <1>;
1906 compatible = "mediatek,mt8186-smi-larb";
1910 clock-names = "apb", "smi";
1911 mediatek,larb-id = <8>;
1913 power-domains = <&spm MT8186_POWER_DOMAIN_WPE>;
1916 imgsys1: clock-controller@15020000 {
1917 compatible = "mediatek,mt8186-imgsys1";
1919 #clock-cells = <1>;
1923 compatible = "mediatek,mt8186-smi-larb";
1927 clock-names = "apb", "smi";
1928 mediatek,larb-id = <9>;
1930 power-domains = <&spm MT8186_POWER_DOMAIN_IMG>;
1933 imgsys2: clock-controller@15820000 {
1934 compatible = "mediatek,mt8186-imgsys2";
1936 #clock-cells = <1>;
1940 compatible = "mediatek,mt8186-smi-larb";
1944 clock-names = "apb", "smi";
1945 mediatek,larb-id = <11>;
1947 power-domains = <&spm MT8186_POWER_DOMAIN_IMG2>;
1951 compatible = "mediatek,mt8186-smi-larb";
1955 clock-names = "apb", "smi";
1956 mediatek,larb-id = <4>;
1958 power-domains = <&spm MT8186_POWER_DOMAIN_VDEC>;
1961 vdecsys: clock-controller@1602f000 {
1962 compatible = "mediatek,mt8186-vdecsys";
1964 #clock-cells = <1>;
1967 vencsys: clock-controller@17000000 { label
1968 compatible = "mediatek,mt8186-vencsys";
1970 #clock-cells = <1>;
1974 compatible = "mediatek,mt8186-smi-larb";
1976 clocks = <&vencsys CLK_VENC_CKE1_VENC>,
1977 <&vencsys CLK_VENC_CKE1_VENC>;
1978 clock-names = "apb", "smi";
1979 mediatek,larb-id = <7>;
1981 power-domains = <&spm MT8186_POWER_DOMAIN_VENC>;
1984 camsys: clock-controller@1a000000 {
1985 compatible = "mediatek,mt8186-camsys";
1987 #clock-cells = <1>;
1991 compatible = "mediatek,mt8186-smi-larb";
1994 clock-names = "apb", "smi";
1995 mediatek,larb-id = <13>;
1997 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2001 compatible = "mediatek,mt8186-smi-larb";
2004 clock-names = "apb", "smi";
2005 mediatek,larb-id = <14>;
2007 power-domains = <&spm MT8186_POWER_DOMAIN_CAM>;
2011 compatible = "mediatek,mt8186-smi-larb";
2015 clock-names = "apb", "smi";
2016 mediatek,larb-id = <16>;
2018 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWA>;
2022 compatible = "mediatek,mt8186-smi-larb";
2026 clock-names = "apb", "smi";
2027 mediatek,larb-id = <17>;
2029 power-domains = <&spm MT8186_POWER_DOMAIN_CAM_RAWB>;
2032 camsys_rawa: clock-controller@1a04f000 {
2033 compatible = "mediatek,mt8186-camsys_rawa";
2035 #clock-cells = <1>;
2038 camsys_rawb: clock-controller@1a06f000 {
2039 compatible = "mediatek,mt8186-camsys_rawb";
2041 #clock-cells = <1>;
2044 mdpsys: clock-controller@1b000000 {
2045 compatible = "mediatek,mt8186-mdpsys";
2047 #clock-cells = <1>;
2051 compatible = "mediatek,mt8186-smi-larb";
2054 clock-names = "apb", "smi";
2055 mediatek,larb-id = <2>;
2057 power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
2060 ipesys: clock-controller@1c000000 {
2061 compatible = "mediatek,mt8186-ipesys";
2063 #clock-cells = <1>;
2067 compatible = "mediatek,mt8186-smi-larb";
2070 clock-names = "apb", "smi";
2071 mediatek,larb-id = <20>;
2073 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;
2077 compatible = "mediatek,mt8186-smi-larb";
2080 clock-names = "apb", "smi";
2081 mediatek,larb-id = <19>;
2083 power-domains = <&spm MT8186_POWER_DOMAIN_IPE>;