Lines Matching +full:mux +full:- +full:gpios
5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/leds/common.h>
17 model = "Bananapi BPI-R64";
18 chassis-type = "embedded";
19 compatible = "bananapi,bpi-r64", "mediatek,mt7622";
26 stdout-path = "serial0:115200n8";
32 proc-supply = <&mt6380_vcpu_reg>;
33 sram-supply = <&mt6380_vm_reg>;
37 proc-supply = <&mt6380_vcpu_reg>;
38 sram-supply = <&mt6380_vm_reg>;
42 gpio-keys {
43 compatible = "gpio-keys";
45 factory-key {
48 gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
51 wps-key {
54 gpios = <&pio 102 GPIO_ACTIVE_LOW>;
59 compatible = "gpio-leds";
61 led-0 {
62 label = "bpi-r64:pio:green";
64 gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
65 default-state = "off";
68 led-1 {
69 label = "bpi-r64:pio:red";
71 gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
72 default-state = "off";
80 reg_1p8v: regulator-1p8v {
81 compatible = "regulator-fixed";
82 regulator-name = "fixed-1.8V";
83 regulator-min-microvolt = <1800000>;
84 regulator-max-microvolt = <1800000>;
85 regulator-always-on;
88 reg_3p3v: regulator-3p3v {
89 compatible = "regulator-fixed";
90 regulator-name = "fixed-3.3V";
91 regulator-min-microvolt = <3300000>;
92 regulator-max-microvolt = <3300000>;
93 regulator-boot-on;
94 regulator-always-on;
97 reg_5v: regulator-5v {
98 compatible = "regulator-fixed";
99 regulator-name = "fixed-5V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-boot-on;
103 regulator-always-on;
116 pinctrl-names = "default";
117 pinctrl-0 = <&irrx_pins>;
124 compatible = "mediatek,eth-mac";
126 phy-mode = "2500base-x";
128 fixed-link {
130 full-duplex;
136 compatible = "mediatek,eth-mac";
138 phy-mode = "rgmii";
140 fixed-link {
142 full-duplex;
147 mdio: mdio-bus {
148 #address-cells = <1>;
149 #size-cells = <0>;
154 interrupt-controller;
155 #interrupt-cells = <1>;
156 interrupt-parent = <&pio>;
158 reset-gpios = <&pio 54 0>;
161 #address-cells = <1>;
162 #size-cells = <0>;
193 phy-mode = "2500base-x";
195 fixed-link {
197 full-duplex;
208 pinctrl-names = "default";
209 pinctrl-0 = <&i2c1_pins>;
214 pinctrl-names = "default";
215 pinctrl-0 = <&i2c2_pins>;
220 pinctrl-names = "default", "state_uhs";
221 pinctrl-0 = <&emmc_pins_default>;
222 pinctrl-1 = <&emmc_pins_uhs>;
224 bus-width = <8>;
225 max-frequency = <50000000>;
226 cap-mmc-highspeed;
227 mmc-hs200-1_8v;
228 vmmc-supply = <®_3p3v>;
229 vqmmc-supply = <®_1p8v>;
230 assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
231 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
232 non-removable;
236 pinctrl-names = "default", "state_uhs";
237 pinctrl-0 = <&sd0_pins_default>;
238 pinctrl-1 = <&sd0_pins_uhs>;
240 bus-width = <4>;
241 max-frequency = <50000000>;
242 cap-sd-highspeed;
243 cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
244 vmmc-supply = <®_3p3v>;
245 vqmmc-supply = <®_3p3v>;
246 assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
247 assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
251 pinctrl-names = "default";
252 pinctrl-0 = <¶llel_nand_pins>;
261 pinctrl-names = "default";
262 pinctrl-0 = <&serial_nand_pins>;
265 compatible = "spi-nand";
267 spi-tx-bus-width = <4>;
268 spi-rx-bus-width = <4>;
269 nand-ecc-engine = <&snfi>;
271 compatible = "fixed-partitions";
272 #address-cells = <1>;
273 #size-cells = <1>;
278 read-only;
284 read-only;
296 pinctrl-names = "default";
297 pinctrl-0 = <&pcie0_pins>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pcie1_pins>;
309 * SATA functions. i.e. output-high: PCIe, output-low: SATA
312 gpio-hog;
313 gpios = <90 GPIO_ACTIVE_HIGH>;
314 output-high;
318 emmc_pins_default: emmc-pins-default {
319 mux {
328 conf-cmd-dat {
332 input-enable;
333 bias-pull-up;
336 conf-clk {
338 bias-pull-down;
342 emmc_pins_uhs: emmc-pins-uhs {
343 mux {
348 conf-cmd-dat {
352 input-enable;
353 drive-strength = <4>;
354 bias-pull-up;
357 conf-clk {
359 drive-strength = <4>;
360 bias-pull-down;
364 eth_pins: eth-pins {
365 mux {
371 i2c1_pins: i2c1-pins {
372 mux {
378 i2c2_pins: i2c2-pins {
379 mux {
385 i2s1_pins: i2s1-pins {
386 mux {
396 drive-strength = <12>;
397 bias-pull-down;
401 irrx_pins: irrx-pins {
402 mux {
408 irtx_pins: irtx-pins {
409 mux {
416 parallel_nand_pins: parallel-nand-pins {
417 mux {
423 pcie0_pins: pcie0-pins {
424 mux {
432 pcie1_pins: pcie1-pins {
433 mux {
441 pmic_bus_pins: pmic-bus-pins {
442 mux {
448 pwm_pins: pwm-pins {
449 mux {
460 wled_pins: wled-pins {
461 mux {
467 sd0_pins_default: sd0-pins-default {
468 mux {
477 conf-cmd-data {
480 input-enable;
481 drive-strength = <8>;
482 bias-pull-up;
484 conf-clk {
486 drive-strength = <12>;
487 bias-pull-down;
489 conf-cd {
491 bias-pull-up;
495 sd0_pins_uhs: sd0-pins-uhs {
496 mux {
501 conf-cmd-data {
504 input-enable;
505 bias-pull-up;
508 conf-clk {
510 bias-pull-down;
514 /* Serial NAND is shared pin with SPI-NOR */
515 serial_nand_pins: serial-nand-pins {
516 mux {
522 spic0_pins: spic0-pins {
523 mux {
529 spic1_pins: spic1-pins {
530 mux {
536 /* SPI-NOR is shared pin with serial NAND */
537 spi_nor_pins: spi-nor-pins {
538 mux {
544 /* serial NAND is shared pin with SPI-NOR */
545 serial_nand_pins: serial-nand-pins {
546 mux {
552 uart0_pins: uart0-pins {
553 mux {
559 uart2_pins: uart2-pins {
560 mux {
566 watchdog_pins: watchdog-pins {
567 mux {
575 pinctrl-names = "default";
576 pinctrl-0 = <&pwm_pins>;
581 pinctrl-names = "default";
582 pinctrl-0 = <&pmic_bus_pins>;
596 pinctrl-names = "default";
597 pinctrl-0 = <&spic0_pins>;
602 pinctrl-names = "default";
603 pinctrl-0 = <&spic1_pins>;
607 vusb33-supply = <®_3p3v>;
608 vbus-supply = <®_5v>;
617 pinctrl-names = "default";
618 pinctrl-0 = <&uart0_pins>;
623 pinctrl-names = "default";
624 pinctrl-0 = <&uart2_pins>;
628 pinctrl-names = "default";
629 pinctrl-0 = <&watchdog_pins>;