Lines Matching +full:psci +full:- +full:0

1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
6  * Copyright (c) 2017-2021 NXP
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 	interrupt-parent = <&gic>;
14 	#address-cells = <2>;
15 	#size-cells = <2>;
18 		#address-cells = <1>;
19 		#size-cells = <0>;
21 		cpu0: cpu@0 {
23 			compatible = "arm,cortex-a53";
24 			reg = <0x0>;
25 			enable-method = "psci";
26 			next-level-cache = <&cluster0_l2>;
31 			compatible = "arm,cortex-a53";
32 			reg = <0x1>;
33 			enable-method = "psci";
34 			next-level-cache = <&cluster0_l2>;
39 			compatible = "arm,cortex-a53";
40 			reg = <0x100>;
41 			enable-method = "psci";
42 			next-level-cache = <&cluster1_l2>;
47 			compatible = "arm,cortex-a53";
48 			reg = <0x101>;
49 			enable-method = "psci";
50 			next-level-cache = <&cluster1_l2>;
53 		cluster0_l2: l2-cache0 {
55 			cache-level = <2>;
56 			cache-unified;
59 		cluster1_l2: l2-cache1 {
61 			cache-level = <2>;
62 			cache-unified;
67 		compatible = "arm,cortex-a53-pmu";
72 		compatible = "arm,armv8-timer";
80 		psci {
81 			compatible = "arm,psci-1.0";
86 	soc@0 {
87 		compatible = "simple-bus";
88 		#address-cells = <1>;
89 		#size-cells = <1>;
90 		ranges = <0 0 0 0x80000000>;
93 			compatible = "nxp,s32g2-linflexuart",
94 				     "fsl,s32v234-linflexuart";
95 			reg = <0x401c8000 0x3000>;
101 			compatible = "nxp,s32g2-linflexuart",
102 				     "fsl,s32v234-linflexuart";
103 			reg = <0x401cc000 0x3000>;
109 			compatible = "nxp,s32g2-linflexuart",
110 				     "fsl,s32v234-linflexuart";
111 			reg = <0x402bc000 0x3000>;
116 		gic: interrupt-controller@50800000 {
117 			compatible = "arm,gic-v3";
118 			reg = <0x50800000 0x10000>,
119 			      <0x50880000 0x80000>,
120 			      <0x50400000 0x2000>,
121 			      <0x50410000 0x2000>,
122 			      <0x50420000 0x2000>;
124 			interrupt-controller;
125 			#interrupt-cells = <3>;