Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright 2017-2020 NXP
8 #include <dt-bindings/clock/imx8-clock.h>
9 #include <dt-bindings/clock/imx8-lpcg.h>
10 #include <dt-bindings/firmware/imx/rsrc.h>
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/interrupt-controller/arm-gic.h>
14 #include <dt-bindings/pinctrl/pads-imx8qxp.h>
15 #include <dt-bindings/thermal/thermal.h>
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
49 vpu-core0 = &vpu_core0;
50 vpu-core1 = &vpu_core1;
51 vpu-core2 = &vpu_core2;
55 #address-cells = <2>;
56 #size-cells = <0>;
58 /* We have 1 clusters with 4 Cortex-A35 cores */
61 compatible = "arm,cortex-a35";
63 enable-method = "psci";
64 i-cache-size = <0x8000>;
65 i-cache-line-size = <64>;
66 i-cache-sets = <256>;
67 d-cache-size = <0x8000>;
68 d-cache-line-size = <64>;
69 d-cache-sets = <128>;
70 next-level-cache = <&A35_L2>;
72 operating-points-v2 = <&a35_opp_table>;
73 #cooling-cells = <2>;
78 compatible = "arm,cortex-a35";
80 enable-method = "psci";
81 i-cache-size = <0x8000>;
82 i-cache-line-size = <64>;
83 i-cache-sets = <256>;
84 d-cache-size = <0x8000>;
85 d-cache-line-size = <64>;
86 d-cache-sets = <128>;
87 next-level-cache = <&A35_L2>;
89 operating-points-v2 = <&a35_opp_table>;
90 #cooling-cells = <2>;
95 compatible = "arm,cortex-a35";
97 enable-method = "psci";
98 i-cache-size = <0x8000>;
99 i-cache-line-size = <64>;
100 i-cache-sets = <256>;
101 d-cache-size = <0x8000>;
102 d-cache-line-size = <64>;
103 d-cache-sets = <128>;
104 next-level-cache = <&A35_L2>;
106 operating-points-v2 = <&a35_opp_table>;
107 #cooling-cells = <2>;
112 compatible = "arm,cortex-a35";
114 enable-method = "psci";
115 i-cache-size = <0x8000>;
116 i-cache-line-size = <64>;
117 i-cache-sets = <256>;
118 d-cache-size = <0x8000>;
119 d-cache-line-size = <64>;
120 d-cache-sets = <128>;
121 next-level-cache = <&A35_L2>;
123 operating-points-v2 = <&a35_opp_table>;
124 #cooling-cells = <2>;
127 A35_L2: l2-cache0 {
129 cache-level = <2>;
130 cache-unified;
131 cache-size = <0x80000>;
132 cache-line-size = <64>;
133 cache-sets = <1024>;
137 a35_opp_table: opp-table {
138 compatible = "operating-points-v2";
139 opp-shared;
141 opp-900000000 {
142 opp-hz = /bits/ 64 <900000000>;
143 opp-microvolt = <1000000>;
144 clock-latency-ns = <150000>;
147 opp-1200000000 {
148 opp-hz = /bits/ 64 <1200000000>;
149 opp-microvolt = <1100000>;
150 clock-latency-ns = <150000>;
151 opp-suspend;
155 gic: interrupt-controller@51a00000 {
156 compatible = "arm,gic-v3";
159 #interrupt-cells = <3>;
160 interrupt-controller;
164 reserved-memory {
165 #address-cells = <2>;
166 #size-cells = <2>;
169 decoder_boot: decoder-boot@84000000 {
171 no-map;
174 encoder_boot: encoder-boot@86000000 {
176 no-map;
179 decoder_rpc: decoder-rpc@92000000 {
181 no-map;
186 no-map;
189 encoder_rpc: encoder-rpc@94400000 {
191 no-map;
196 compatible = "arm,cortex-a35-pmu";
201 compatible = "arm,psci-1.0";
205 system-controller {
206 compatible = "fsl,imx-scu";
207 mbox-names = "tx0",
214 pd: power-controller {
215 compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
216 #power-domain-cells = <1>;
219 clk: clock-controller {
220 compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
221 #clock-cells = <2>;
225 compatible = "fsl,imx8qxp-iomuxc";
229 compatible = "fsl,imx8qxp-scu-ocotp";
230 #address-cells = <1>;
231 #size-cells = <1>;
235 compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
241 compatible = "fsl,imx8qxp-sc-rtc";
245 compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
246 timeout-sec = <60>;
249 tsens: thermal-sensor {
250 compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
251 #thermal-sensor-cells = <1>;
256 compatible = "arm,armv8-timer";
258 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Physical Non-Secure */
263 xtal32k: clock-xtal32k {
264 compatible = "fixed-clock";
265 #clock-cells = <0>;
266 clock-frequency = <32768>;
267 clock-output-names = "xtal_32KHz";
270 xtal24m: clock-xtal24m {
271 compatible = "fixed-clock";
272 #clock-cells = <0>;
273 clock-frequency = <24000000>;
274 clock-output-names = "xtal_24MHz";
277 thermal_zones: thermal-zones {
278 cpu0-thermal {
279 polling-delay-passive = <250>;
280 polling-delay = <2000>;
281 thermal-sensors = <&tsens IMX_SC_R_SYSTEM>;
297 cooling-maps {
300 cooling-device =
311 #include "imx8-ss-img.dtsi"
312 #include "imx8-ss-vpu.dtsi"
313 #include "imx8-ss-adma.dtsi"
314 #include "imx8-ss-conn.dtsi"
315 #include "imx8-ss-ddr.dtsi"
316 #include "imx8-ss-lsio.dtsi"
319 #include "imx8qxp-ss-img.dtsi"
320 #include "imx8qxp-ss-adma.dtsi"
321 #include "imx8qxp-ss-conn.dtsi"
322 #include "imx8qxp-ss-lsio.dtsi"