Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
8 uart4_lpcg: clock-controller@5a4a0000 {
9 compatible = "fsl,imx8qxp-lpcg";
11 #clock-cells = <1>;
14 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
15 clock-output-names = "uart4_lpcg_baud_clk",
17 power-domains = <&pd IMX_SC_R_UART_4>;
20 can1_lpcg: clock-controller@5ace0000 {
21 compatible = "fsl,imx8qxp-lpcg";
23 #clock-cells = <1>;
26 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
27 clock-output-names = "can1_lpcg_pe_clk",
30 power-domains = <&pd IMX_SC_R_CAN_1>;
33 can2_lpcg: clock-controller@5acf0000 {
34 compatible = "fsl,imx8qxp-lpcg";
36 #clock-cells = <1>;
39 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>;
40 clock-output-names = "can2_lpcg_pe_clk",
43 power-domains = <&pd IMX_SC_R_CAN_2>;
48 fsl,clk-source = /bits/ 8 <1>;
54 assigned-clocks = <&clk IMX_SC_R_CAN_1 IMX_SC_PM_CLK_PER>;
55 fsl,clk-source = /bits/ 8 <1>;
61 assigned-clocks = <&clk IMX_SC_R_CAN_2 IMX_SC_PM_CLK_PER>;
62 fsl,clk-source = /bits/ 8 <1>;
66 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
70 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
74 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
78 compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart";
82 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
86 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
90 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
94 compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";