Lines Matching +full:aips +full:- +full:bus
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mp-clock.h>
7 #include <dt-bindings/power/imx8mp-power.h>
8 #include <dt-bindings/reset/imx8mp-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interconnect/fsl,imx8mp.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/thermal/thermal.h>
15 #include "imx8mp-pinfunc.h"
18 interrupt-parent = <&gic>;
19 #address-cells = <2>;
20 #size-cells = <2>;
47 #address-cells = <1>;
48 #size-cells = <0>;
52 compatible = "arm,cortex-a53";
54 clock-latency = <61036>;
56 enable-method = "psci";
57 i-cache-size = <0x8000>;
58 i-cache-line-size = <64>;
59 i-cache-sets = <256>;
60 d-cache-size = <0x8000>;
61 d-cache-line-size = <64>;
62 d-cache-sets = <128>;
63 next-level-cache = <&A53_L2>;
64 nvmem-cells = <&cpu_speed_grade>;
65 nvmem-cell-names = "speed_grade";
66 operating-points-v2 = <&a53_opp_table>;
67 #cooling-cells = <2>;
72 compatible = "arm,cortex-a53";
74 clock-latency = <61036>;
76 enable-method = "psci";
77 i-cache-size = <0x8000>;
78 i-cache-line-size = <64>;
79 i-cache-sets = <256>;
80 d-cache-size = <0x8000>;
81 d-cache-line-size = <64>;
82 d-cache-sets = <128>;
83 next-level-cache = <&A53_L2>;
84 operating-points-v2 = <&a53_opp_table>;
85 #cooling-cells = <2>;
90 compatible = "arm,cortex-a53";
92 clock-latency = <61036>;
94 enable-method = "psci";
95 i-cache-size = <0x8000>;
96 i-cache-line-size = <64>;
97 i-cache-sets = <256>;
98 d-cache-size = <0x8000>;
99 d-cache-line-size = <64>;
100 d-cache-sets = <128>;
101 next-level-cache = <&A53_L2>;
102 operating-points-v2 = <&a53_opp_table>;
103 #cooling-cells = <2>;
108 compatible = "arm,cortex-a53";
110 clock-latency = <61036>;
112 enable-method = "psci";
113 i-cache-size = <0x8000>;
114 i-cache-line-size = <64>;
115 i-cache-sets = <256>;
116 d-cache-size = <0x8000>;
117 d-cache-line-size = <64>;
118 d-cache-sets = <128>;
119 next-level-cache = <&A53_L2>;
120 operating-points-v2 = <&a53_opp_table>;
121 #cooling-cells = <2>;
124 A53_L2: l2-cache0 {
126 cache-unified;
127 cache-level = <2>;
128 cache-size = <0x80000>;
129 cache-line-size = <64>;
130 cache-sets = <512>;
134 a53_opp_table: opp-table {
135 compatible = "operating-points-v2";
136 opp-shared;
138 opp-1200000000 {
139 opp-hz = /bits/ 64 <1200000000>;
140 opp-microvolt = <850000>;
141 opp-supported-hw = <0x8a0>, <0x7>;
142 clock-latency-ns = <150000>;
143 opp-suspend;
146 opp-1600000000 {
147 opp-hz = /bits/ 64 <1600000000>;
148 opp-microvolt = <950000>;
149 opp-supported-hw = <0xa0>, <0x7>;
150 clock-latency-ns = <150000>;
151 opp-suspend;
154 opp-1800000000 {
155 opp-hz = /bits/ 64 <1800000000>;
156 opp-microvolt = <1000000>;
157 opp-supported-hw = <0x20>, <0x3>;
158 clock-latency-ns = <150000>;
159 opp-suspend;
163 osc_32k: clock-osc-32k {
164 compatible = "fixed-clock";
165 #clock-cells = <0>;
166 clock-frequency = <32768>;
167 clock-output-names = "osc_32k";
170 osc_24m: clock-osc-24m {
171 compatible = "fixed-clock";
172 #clock-cells = <0>;
173 clock-frequency = <24000000>;
174 clock-output-names = "osc_24m";
177 clk_ext1: clock-ext1 {
178 compatible = "fixed-clock";
179 #clock-cells = <0>;
180 clock-frequency = <133000000>;
181 clock-output-names = "clk_ext1";
184 clk_ext2: clock-ext2 {
185 compatible = "fixed-clock";
186 #clock-cells = <0>;
187 clock-frequency = <133000000>;
188 clock-output-names = "clk_ext2";
191 clk_ext3: clock-ext3 {
192 compatible = "fixed-clock";
193 #clock-cells = <0>;
194 clock-frequency = <133000000>;
195 clock-output-names = "clk_ext3";
198 clk_ext4: clock-ext4 {
199 compatible = "fixed-clock";
200 #clock-cells = <0>;
201 clock-frequency = <133000000>;
202 clock-output-names = "clk_ext4";
205 reserved-memory {
206 #address-cells = <2>;
207 #size-cells = <2>;
212 no-map;
217 compatible = "arm,cortex-a53-pmu";
223 compatible = "arm,psci-1.0";
227 thermal-zones {
228 cpu-thermal {
229 polling-delay-passive = <250>;
230 polling-delay = <2000>;
231 thermal-sensors = <&tmu 0>;
246 cooling-maps {
249 cooling-device =
258 soc-thermal {
259 polling-delay-passive = <250>;
260 polling-delay = <2000>;
261 thermal-sensors = <&tmu 1>;
276 cooling-maps {
279 cooling-device =
290 compatible = "arm,armv8-timer";
295 clock-frequency = <8000000>;
296 arm,no-tick-in-suspend;
300 compatible = "fsl,imx8mp-soc", "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
304 nvmem-cells = <&imx8mp_uid>;
305 nvmem-cell-names = "soc_unique_id";
308 compatible = "arm,coresight-etm4x", "arm,primecell";
312 clock-names = "apb_pclk";
314 out-ports {
317 remote-endpoint = <&ca_funnel_in_port0>;
324 compatible = "arm,coresight-etm4x", "arm,primecell";
328 clock-names = "apb_pclk";
330 out-ports {
333 remote-endpoint = <&ca_funnel_in_port1>;
340 compatible = "arm,coresight-etm4x", "arm,primecell";
344 clock-names = "apb_pclk";
346 out-ports {
349 remote-endpoint = <&ca_funnel_in_port2>;
356 compatible = "arm,coresight-etm4x", "arm,primecell";
360 clock-names = "apb_pclk";
362 out-ports {
365 remote-endpoint = <&ca_funnel_in_port3>;
373 * non-configurable funnel don't show up on the AMBA
374 * bus. As such no need to add "arm,primecell".
376 compatible = "arm,coresight-static-funnel";
378 in-ports {
379 #address-cells = <1>;
380 #size-cells = <0>;
386 remote-endpoint = <&etm0_out_port>;
394 remote-endpoint = <&etm1_out_port>;
402 remote-endpoint = <&etm2_out_port>;
410 remote-endpoint = <&etm3_out_port>;
415 out-ports {
418 remote-endpoint = <&hugo_funnel_in_port0>;
425 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
428 clock-names = "apb_pclk";
430 in-ports {
431 #address-cells = <1>;
432 #size-cells = <0>;
438 remote-endpoint = <&ca_funnel_out_port0>;
460 out-ports {
463 remote-endpoint = <&etf_in_port>;
470 compatible = "arm,coresight-tmc", "arm,primecell";
473 clock-names = "apb_pclk";
475 in-ports {
478 remote-endpoint = <&hugo_funnel_out_port0>;
483 out-ports {
486 remote-endpoint = <&etr_in_port>;
493 compatible = "arm,coresight-tmc", "arm,primecell";
496 clock-names = "apb_pclk";
498 in-ports {
501 remote-endpoint = <&etf_out_port>;
507 aips1: bus@30000000 {
508 compatible = "fsl,aips-bus", "simple-bus";
510 #address-cells = <1>;
511 #size-cells = <1>;
515 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
520 gpio-controller;
521 #gpio-cells = <2>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 gpio-ranges = <&iomuxc 0 5 30>;
528 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
533 gpio-controller;
534 #gpio-cells = <2>;
535 interrupt-controller;
536 #interrupt-cells = <2>;
537 gpio-ranges = <&iomuxc 0 35 21>;
541 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
546 gpio-controller;
547 #gpio-cells = <2>;
548 interrupt-controller;
549 #interrupt-cells = <2>;
550 gpio-ranges = <&iomuxc 0 56 26>, <&iomuxc 26 144 4>;
554 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
559 gpio-controller;
560 #gpio-cells = <2>;
561 interrupt-controller;
562 #interrupt-cells = <2>;
563 gpio-ranges = <&iomuxc 0 82 32>;
567 compatible = "fsl,imx8mp-gpio", "fsl,imx35-gpio";
572 gpio-controller;
573 #gpio-cells = <2>;
574 interrupt-controller;
575 #interrupt-cells = <2>;
576 gpio-ranges = <&iomuxc 0 114 30>;
580 compatible = "fsl,imx8mp-tmu";
583 nvmem-cells = <&tmu_calib>;
584 nvmem-cell-names = "calib";
585 #thermal-sensor-cells = <1>;
589 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
597 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
605 compatible = "fsl,imx8mp-wdt", "fsl,imx21-wdt";
613 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
617 clock-names = "ipg", "per";
621 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
625 clock-names = "ipg", "per";
629 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
633 clock-names = "ipg", "per";
637 compatible = "fsl,imx8mp-iomuxc";
642 compatible = "fsl,imx8mp-iomuxc-gpr", "syscon";
647 compatible = "fsl,imx8mp-ocotp", "fsl,imx8mm-ocotp", "syscon";
651 #address-cells = <1>;
652 #size-cells = <1>;
667 imx8mp_uid: unique-id@8 { /* 0x420-0x430 */
671 cpu_speed_grade: speed-grade@10 { /* 0x440 */
675 eth_mac1: mac-address@90 { /* 0x640 */
679 eth_mac2: mac-address@96 { /* 0x658 */
683 tmu_calib: calib@264 { /* 0xd90-0xdc0 */
688 anatop: clock-controller@30360000 {
689 compatible = "fsl,imx8mp-anatop", "fsl,imx8mm-anatop";
691 #clock-cells = <1>;
695 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
698 snvs_rtc: snvs-rtc-lp {
699 compatible = "fsl,sec-v4.0-mon-rtc-lp";
705 clock-names = "snvs-rtc";
708 snvs_pwrkey: snvs-powerkey {
709 compatible = "fsl,sec-v4.0-pwrkey";
713 clock-names = "snvs-pwrkey";
715 wakeup-source;
719 snvs_lpgpr: snvs-lpgpr {
720 compatible = "fsl,imx8mp-snvs-lpgpr",
721 "fsl,imx7d-snvs-lpgpr";
725 clk: clock-controller@30380000 {
726 compatible = "fsl,imx8mp-ccm";
728 #clock-cells = <1>;
731 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
733 assigned-clocks = <&clk IMX8MP_CLK_A53_SRC>,
738 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
743 assigned-clock-rates = <0>, <0>,
749 src: reset-controller@30390000 {
750 compatible = "fsl,imx8mp-src", "syscon";
753 #reset-cells = <1>;
757 compatible = "fsl,imx8mp-gpc";
759 interrupt-parent = <&gic>;
761 interrupt-controller;
762 #interrupt-cells = <3>;
765 #address-cells = <1>;
766 #size-cells = <0>;
768 pgc_mipi_phy1: power-domain@0 {
769 #power-domain-cells = <0>;
773 pgc_pcie_phy: power-domain@1 {
774 #power-domain-cells = <0>;
778 pgc_usb1_phy: power-domain@2 {
779 #power-domain-cells = <0>;
783 pgc_usb2_phy: power-domain@3 {
784 #power-domain-cells = <0>;
788 pgc_audio: power-domain@5 {
789 #power-domain-cells = <0>;
793 assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>,
795 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
797 assigned-clock-rates = <400000000>,
801 pgc_gpu2d: power-domain@6 {
802 #power-domain-cells = <0>;
805 power-domains = <&pgc_gpumix>;
808 pgc_gpumix: power-domain@7 {
809 #power-domain-cells = <0>;
813 assigned-clocks = <&clk IMX8MP_CLK_GPU_AXI>,
815 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
817 assigned-clock-rates = <800000000>, <400000000>;
820 pgc_gpu3d: power-domain@9 {
821 #power-domain-cells = <0>;
825 power-domains = <&pgc_gpumix>;
828 pgc_mediamix: power-domain@10 {
829 #power-domain-cells = <0>;
835 pgc_mipi_phy2: power-domain@16 {
836 #power-domain-cells = <0>;
840 pgc_hsiomix: power-domain@17 {
841 #power-domain-cells = <0>;
845 assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
846 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
847 assigned-clock-rates = <500000000>;
850 pgc_ispdwp: power-domain@18 {
851 #power-domain-cells = <0>;
856 pgc_vpumix: power-domain@19 {
857 #power-domain-cells = <0>;
862 pgc_vpu_g1: power-domain@20 {
863 #power-domain-cells = <0>;
864 power-domains = <&pgc_vpumix>;
869 pgc_vpu_g2: power-domain@21 {
870 #power-domain-cells = <0>;
871 power-domains = <&pgc_vpumix>;
876 pgc_vpu_vc8000e: power-domain@22 {
877 #power-domain-cells = <0>;
878 power-domains = <&pgc_vpumix>;
883 pgc_mlmix: power-domain@24 {
884 #power-domain-cells = <0>;
894 aips2: bus@30400000 {
895 compatible = "fsl,aips-bus", "simple-bus";
897 #address-cells = <1>;
898 #size-cells = <1>;
902 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
907 clock-names = "ipg", "per";
908 #pwm-cells = <3>;
913 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
918 clock-names = "ipg", "per";
919 #pwm-cells = <3>;
924 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
929 clock-names = "ipg", "per";
930 #pwm-cells = <3>;
935 compatible = "fsl,imx8mp-pwm", "fsl,imx27-pwm";
940 clock-names = "ipg", "per";
941 #pwm-cells = <3>;
946 compatible = "nxp,sysctr-timer";
950 clock-names = "per";
954 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
958 clock-names = "ipg", "per";
962 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
966 clock-names = "ipg", "per";
970 compatible = "fsl,imx8mp-gpt", "fsl,imx6dl-gpt";
974 clock-names = "ipg", "per";
978 aips3: bus@30800000 {
979 compatible = "fsl,aips-bus", "simple-bus";
981 #address-cells = <1>;
982 #size-cells = <1>;
985 spba-bus@30800000 {
986 compatible = "fsl,spba-bus", "simple-bus";
988 #address-cells = <1>;
989 #size-cells = <1>;
993 #address-cells = <1>;
994 #size-cells = <0>;
995 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1000 clock-names = "ipg", "per";
1001 assigned-clock-rates = <80000000>;
1002 assigned-clocks = <&clk IMX8MP_CLK_ECSPI1>;
1003 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1005 dma-names = "rx", "tx";
1010 #address-cells = <1>;
1011 #size-cells = <0>;
1012 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1017 clock-names = "ipg", "per";
1018 assigned-clock-rates = <80000000>;
1019 assigned-clocks = <&clk IMX8MP_CLK_ECSPI2>;
1020 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1022 dma-names = "rx", "tx";
1027 #address-cells = <1>;
1028 #size-cells = <0>;
1029 compatible = "fsl,imx8mp-ecspi", "fsl,imx6ul-ecspi";
1034 clock-names = "ipg", "per";
1035 assigned-clock-rates = <80000000>;
1036 assigned-clocks = <&clk IMX8MP_CLK_ECSPI3>;
1037 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1039 dma-names = "rx", "tx";
1044 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1049 clock-names = "ipg", "per";
1051 dma-names = "rx", "tx";
1056 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1061 clock-names = "ipg", "per";
1063 dma-names = "rx", "tx";
1068 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1073 clock-names = "ipg", "per";
1075 dma-names = "rx", "tx";
1080 compatible = "fsl,imx8mp-flexcan";
1085 clock-names = "ipg", "per";
1086 assigned-clocks = <&clk IMX8MP_CLK_CAN1>;
1087 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1088 assigned-clock-rates = <40000000>;
1089 fsl,clk-source = /bits/ 8 <0>;
1090 fsl,stop-mode = <&gpr 0x10 4>;
1095 compatible = "fsl,imx8mp-flexcan";
1100 clock-names = "ipg", "per";
1101 assigned-clocks = <&clk IMX8MP_CLK_CAN2>;
1102 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_40M>;
1103 assigned-clock-rates = <40000000>;
1104 fsl,clk-source = /bits/ 8 <0>;
1105 fsl,stop-mode = <&gpr 0x10 5>;
1111 compatible = "fsl,sec-v4.0";
1112 #address-cells = <1>;
1113 #size-cells = <1>;
1119 clock-names = "aclk", "ipg";
1122 compatible = "fsl,sec-v4.0-job-ring";
1129 compatible = "fsl,sec-v4.0-job-ring";
1135 compatible = "fsl,sec-v4.0-job-ring";
1142 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1143 #address-cells = <1>;
1144 #size-cells = <0>;
1152 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1153 #address-cells = <1>;
1154 #size-cells = <0>;
1162 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1163 #address-cells = <1>;
1164 #size-cells = <0>;
1172 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1173 #address-cells = <1>;
1174 #size-cells = <0>;
1182 compatible = "fsl,imx8mp-uart", "fsl,imx6q-uart";
1187 clock-names = "ipg", "per";
1189 dma-names = "rx", "tx";
1194 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1198 #mbox-cells = <2>;
1202 compatible = "fsl,imx8mp-mu", "fsl,imx6sx-mu";
1205 #mbox-cells = <2>;
1210 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1211 #address-cells = <1>;
1212 #size-cells = <0>;
1220 compatible = "fsl,imx8mp-i2c", "fsl,imx21-i2c";
1221 #address-cells = <1>;
1222 #size-cells = <0>;
1230 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1236 clock-names = "ipg", "ahb", "per";
1237 fsl,tuning-start-tap = <20>;
1238 fsl,tuning-step = <2>;
1239 bus-width = <4>;
1244 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1250 clock-names = "ipg", "ahb", "per";
1251 fsl,tuning-start-tap = <20>;
1252 fsl,tuning-step = <2>;
1253 bus-width = <4>;
1258 compatible = "fsl,imx8mp-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1264 clock-names = "ipg", "ahb", "per";
1265 fsl,tuning-start-tap = <20>;
1266 fsl,tuning-step = <2>;
1267 bus-width = <4>;
1272 compatible = "nxp,imx8mp-fspi";
1274 reg-names = "fspi_base", "fspi_mmap";
1278 clock-names = "fspi_en", "fspi";
1279 assigned-clock-rates = <80000000>;
1280 assigned-clocks = <&clk IMX8MP_CLK_QSPI>;
1281 #address-cells = <1>;
1282 #size-cells = <0>;
1286 sdma1: dma-controller@30bd0000 {
1287 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1292 clock-names = "ipg", "ahb";
1293 #dma-cells = <3>;
1294 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1298 compatible = "fsl,imx8mp-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1309 clock-names = "ipg", "ahb", "ptp",
1311 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1315 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1319 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1320 fsl,num-tx-queues = <3>;
1321 fsl,num-rx-queues = <3>;
1322 nvmem-cells = <ð_mac1>;
1323 nvmem-cell-names = "mac-address";
1324 fsl,stop-mode = <&gpr 0x10 3>;
1329 compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
1333 interrupt-names = "macirq", "eth_wake_irq";
1338 clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
1339 assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
1342 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
1345 assigned-clock-rates = <0>, <100000000>, <125000000>;
1346 nvmem-cells = <ð_mac2>;
1347 nvmem-cell-names = "mac-address";
1353 aips5: bus@30c00000 {
1354 compatible = "fsl,aips-bus", "simple-bus";
1356 #address-cells = <1>;
1357 #size-cells = <1>;
1360 spba-bus@30c00000 {
1361 compatible = "fsl,spba-bus", "simple-bus";
1363 #address-cells = <1>;
1364 #size-cells = <1>;
1368 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1370 #sound-dai-cells = <0>;
1376 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1378 dma-names = "rx", "tx";
1384 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1386 #sound-dai-cells = <0>;
1392 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1394 dma-names = "rx", "tx";
1400 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1402 #sound-dai-cells = <0>;
1408 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1410 dma-names = "rx", "tx";
1416 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1418 #sound-dai-cells = <0>;
1424 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1426 dma-names = "rx", "tx";
1432 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1434 #sound-dai-cells = <0>;
1440 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1442 dma-names = "rx", "tx";
1448 compatible = "fsl,imx8mp-sai", "fsl,imx8mq-sai";
1450 #sound-dai-cells = <0>;
1456 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
1458 dma-names = "rx", "tx";
1464 sdma3: dma-controller@30e00000 {
1465 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1467 #dma-cells = <3>;
1470 clock-names = "ipg", "ahb";
1472 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1475 sdma2: dma-controller@30e10000 {
1476 compatible = "fsl,imx8mp-sdma", "fsl,imx8mq-sdma";
1478 #dma-cells = <3>;
1481 clock-names = "ipg", "ahb";
1483 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1486 audio_blk_ctrl: clock-controller@30e20000 {
1487 compatible = "fsl,imx8mp-audio-blk-ctrl";
1489 #clock-cells = <1>;
1497 clock-names = "ahb",
1500 power-domains = <&pgc_audio>;
1505 compatible = "fsl,imx8mp-noc", "fsl,imx8m-noc";
1508 #interconnect-cells = <1>;
1509 operating-points-v2 = <&noc_opp_table>;
1511 noc_opp_table: opp-table {
1512 compatible = "operating-points-v2";
1514 opp-200000000 {
1515 opp-hz = /bits/ 64 <200000000>;
1518 opp-1000000000 {
1519 opp-hz = /bits/ 64 <1000000000>;
1524 aips4: bus@32c00000 {
1525 compatible = "fsl,aips-bus", "simple-bus";
1527 #address-cells = <1>;
1528 #size-cells = <1>;
1532 compatible = "fsl,imx8mp-isi";
1538 clock-names = "axi", "apb";
1539 fsl,blk-ctrl = <&media_blk_ctrl>;
1540 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_ISI>;
1544 #address-cells = <1>;
1545 #size-cells = <0>;
1551 remote-endpoint = <&mipi_csi_0_out>;
1559 remote-endpoint = <&mipi_csi_1_out>;
1566 compatible = "nxp,imx8mp-dw100";
1571 clock-names = "axi", "ahb";
1572 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_DWE>;
1576 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1579 clock-frequency = <500000000>;
1584 clock-names = "pclk", "wrap", "phy", "axi";
1585 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM1_PIX>;
1586 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1587 assigned-clock-rates = <500000000>;
1588 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_1>;
1592 #address-cells = <1>;
1593 #size-cells = <0>;
1603 remote-endpoint = <&isi_in_0>;
1610 compatible = "fsl,imx8mp-mipi-csi2", "fsl,imx8mm-mipi-csi2";
1613 clock-frequency = <266000000>;
1618 clock-names = "pclk", "wrap", "phy", "axi";
1619 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_CAM2_PIX>;
1620 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1621 assigned-clock-rates = <266000000>;
1622 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_CSI2_2>;
1626 #address-cells = <1>;
1627 #size-cells = <0>;
1637 remote-endpoint = <&isi_in_1>;
1644 compatible = "fsl,imx8mp-mipi-dsim";
1648 clock-names = "bus_clk", "sclk_mipi";
1649 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_APB>,
1651 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1653 assigned-clock-rates = <200000000>, <24000000>;
1654 samsung,pll-clock-frequency = <24000000>;
1656 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_MIPI_DSI_1>;
1660 #address-cells = <1>;
1661 #size-cells = <0>;
1667 remote-endpoint = <&lcdif1_to_dsim>;
1673 lcdif1: display-controller@32e80000 {
1674 compatible = "fsl,imx8mp-lcdif";
1679 clock-names = "pix", "axi", "disp_axi";
1681 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_1>;
1686 remote-endpoint = <&dsim_from_lcdif1>;
1691 lcdif2: display-controller@32e90000 {
1692 compatible = "fsl,imx8mp-lcdif";
1698 clock-names = "pix", "axi", "disp_axi";
1699 power-domains = <&media_blk_ctrl IMX8MP_MEDIABLK_PD_LCDIF_2>;
1704 remote-endpoint = <&ldb_from_lcdif2>;
1709 media_blk_ctrl: blk-ctrl@32ec0000 {
1710 compatible = "fsl,imx8mp-media-blk-ctrl",
1713 #address-cells = <1>;
1714 #size-cells = <1>;
1715 power-domains = <&pgc_mediamix>,
1725 power-domain-names = "bus", "mipi-dsi1", "mipi-csi1",
1726 "lcdif1", "isi", "mipi-csi2",
1728 "mipi-dsi2";
1738 interconnect-names = "lcdif-rd", "lcdif-wr", "isi0",
1749 clock-names = "apb", "axi", "cam1", "cam2",
1752 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_AXI>,
1757 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>,
1761 assigned-clock-rates = <500000000>, <200000000>,
1763 #power-domain-cells = <1>;
1766 compatible = "fsl,imx8mp-ldb";
1768 reg-names = "ldb", "lvds";
1770 clock-names = "ldb";
1771 assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>;
1772 assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>;
1776 #address-cells = <1>;
1777 #size-cells = <0>;
1783 remote-endpoint = <&lcdif2_to_ldb>;
1804 pcie_phy: pcie-phy@32f00000 {
1805 compatible = "fsl,imx8mp-pcie-phy";
1809 reset-names = "pciephy", "perst";
1810 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE_PHY>;
1811 #phy-cells = <0>;
1815 hsio_blk_ctrl: blk-ctrl@32f10000 {
1816 compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
1820 clock-names = "usb", "pcie";
1821 power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
1824 power-domain-names = "bus", "usb", "usb-phy1",
1825 "usb-phy2", "pcie", "pcie-phy";
1830 interconnect-names = "noc-pcie", "usb1", "usb2", "pcie";
1831 #power-domain-cells = <1>;
1832 #clock-cells = <0>;
1837 compatible = "fsl,imx8mp-pcie";
1839 reg-names = "dbi", "config";
1843 clock-names = "pcie", "pcie_bus", "pcie_aux";
1844 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1845 assigned-clock-rates = <10000000>;
1846 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1847 #address-cells = <3>;
1848 #size-cells = <2>;
1850 bus-range = <0x00 0xff>;
1852 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1853 num-lanes = <1>;
1854 num-viewport = <4>;
1856 interrupt-names = "msi";
1857 #interrupt-cells = <1>;
1858 interrupt-map-mask = <0 0 0 0x7>;
1859 interrupt-map = <0 0 0 1 &gic GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
1863 fsl,max-link-speed = <3>;
1864 linux,pci-domain = <0>;
1865 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1868 reset-names = "apps", "turnoff";
1870 phy-names = "pcie-phy";
1874 pcie_ep: pcie-ep@33800000 {
1875 compatible = "fsl,imx8mp-pcie-ep";
1877 reg-names = "dbi", "addr_space";
1881 clock-names = "pcie", "pcie_bus", "pcie_aux";
1882 assigned-clocks = <&clk IMX8MP_CLK_PCIE_AUX>;
1883 assigned-clock-rates = <10000000>;
1884 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_50M>;
1885 num-lanes = <1>;
1887 interrupt-names = "dma";
1888 fsl,max-link-speed = <3>;
1889 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_PCIE>;
1892 reset-names = "apps", "turnoff";
1894 phy-names = "pcie-phy";
1895 num-ib-windows = <4>;
1896 num-ob-windows = <4>;
1908 clock-names = "core", "shader", "bus", "reg";
1909 assigned-clocks = <&clk IMX8MP_CLK_GPU3D_CORE>,
1911 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>,
1913 assigned-clock-rates = <800000000>, <800000000>;
1914 power-domains = <&pgc_gpu3d>;
1924 clock-names = "core", "bus", "reg";
1925 assigned-clocks = <&clk IMX8MP_CLK_GPU2D_CORE>;
1926 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>;
1927 assigned-clock-rates = <800000000>;
1928 power-domains = <&pgc_gpu2d>;
1931 vpu_g1: video-codec@38300000 {
1932 compatible = "nxp,imx8mm-vpu-g1";
1936 assigned-clocks = <&clk IMX8MP_CLK_VPU_G1>;
1937 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1938 assigned-clock-rates = <600000000>;
1939 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G1>;
1942 vpu_g2: video-codec@38310000 {
1943 compatible = "nxp,imx8mq-vpu-g2";
1947 assigned-clocks = <&clk IMX8MP_CLK_VPU_G2>;
1948 assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_1000M>;
1949 assigned-clock-rates = <500000000>;
1950 power-domains = <&vpumix_blk_ctrl IMX8MP_VPUBLK_PD_G2>;
1953 vpumix_blk_ctrl: blk-ctrl@38330000 {
1954 compatible = "fsl,imx8mp-vpu-blk-ctrl", "syscon";
1956 #power-domain-cells = <1>;
1957 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1959 power-domain-names = "bus", "g1", "g2", "vc8000e";
1963 clock-names = "g1", "g2", "vc8000e";
1964 assigned-clocks = <&clk IMX8MP_CLK_VPU_BUS>, <&clk IMX8MP_VPU_PLL>;
1965 assigned-clock-parents = <&clk IMX8MP_VPU_PLL_OUT>;
1966 assigned-clock-rates = <600000000>, <600000000>;
1970 interconnect-names = "g1", "g2", "vc8000e";
1973 gic: interrupt-controller@38800000 {
1974 compatible = "arm,gic-v3";
1977 #interrupt-cells = <3>;
1978 interrupt-controller;
1980 interrupt-parent = <&gic>;
1983 edacmc: memory-controller@3d400000 {
1984 compatible = "snps,ddrc-3.80a";
1989 ddr-pmu@3d800000 {
1990 compatible = "fsl,imx8mp-ddr-pmu", "fsl,imx8m-ddr-pmu";
1995 usb3_phy0: usb-phy@381f0040 {
1996 compatible = "fsl,imx8mp-usb-phy";
1999 clock-names = "phy";
2000 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2001 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2002 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
2003 #phy-cells = <0>;
2008 compatible = "fsl,imx8mp-dwc3";
2013 clock-names = "hsio", "suspend";
2015 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2016 #address-cells = <1>;
2017 #size-cells = <1>;
2018 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2028 clock-names = "bus_early", "ref", "suspend";
2031 phy-names = "usb2-phy", "usb3-phy";
2032 snps,gfladj-refclk-lpm-sel-quirk;
2037 usb3_phy1: usb-phy@382f0040 {
2038 compatible = "fsl,imx8mp-usb-phy";
2041 clock-names = "phy";
2042 assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
2043 assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
2044 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
2045 #phy-cells = <0>;
2050 compatible = "fsl,imx8mp-dwc3";
2055 clock-names = "hsio", "suspend";
2057 power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
2058 #address-cells = <1>;
2059 #size-cells = <1>;
2060 dma-ranges = <0x40000000 0x40000000 0xc0000000>;
2070 clock-names = "bus_early", "ref", "suspend";
2073 phy-names = "usb2-phy", "usb3-phy";
2074 snps,gfladj-refclk-lpm-sel-quirk;
2079 compatible = "fsl,imx8mp-dsp";
2081 mbox-names = "txdb0", "txdb1",
2085 memory-region = <&dsp_reserved>;