Lines Matching +full:imx8mm +full:- +full:micfil
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mn-clock.h>
7 #include <dt-bindings/power/imx8mn-power.h>
8 #include <dt-bindings/reset/imx8mq-reset.h>
9 #include <dt-bindings/gpio/gpio.h>
10 #include <dt-bindings/input/input.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mn-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>;
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>;
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>;
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>;
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-unified;
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0xb00>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
161 opp-1400000000 {
162 opp-hz = /bits/ 64 <1400000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0x300>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
169 opp-1500000000 {
170 opp-hz = /bits/ 64 <1500000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x100>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
221 compatible = "arm,cortex-a53-pmu";
227 compatible = "arm,psci-1.0";
231 thermal-zones {
232 cpu-thermal {
233 polling-delay-passive = <250>;
234 polling-delay = <2000>;
235 thermal-sensors = <&tmu>;
250 cooling-maps {
253 cooling-device =
264 compatible = "arm,armv8-timer";
269 clock-frequency = <8000000>;
270 arm,no-tick-in-suspend;
274 compatible = "fsl,imx8mn-soc", "simple-bus";
275 #address-cells = <1>;
276 #size-cells = <1>;
278 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
279 nvmem-cells = <&imx8mn_uid>;
280 nvmem-cell-names = "soc_unique_id";
283 compatible = "fsl,aips-bus", "simple-bus";
285 #address-cells = <1>;
286 #size-cells = <1>;
289 spba2: spba-bus@30000000 {
290 compatible = "fsl,spba-bus", "simple-bus";
291 #address-cells = <1>;
292 #size-cells = <1>;
297 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
299 #sound-dai-cells = <0>;
305 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
307 dma-names = "rx", "tx";
312 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
314 #sound-dai-cells = <0>;
320 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
322 dma-names = "rx", "tx";
327 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
329 #sound-dai-cells = <0>;
335 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
337 dma-names = "rx", "tx";
338 fsl,shared-interrupt;
344 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
346 #sound-dai-cells = <0>;
352 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
358 micfil: audio-controller@30080000 { label
359 compatible = "fsl,imx8mm-micfil";
370 clock-names = "ipg_clk", "ipg_clk_app",
373 dma-names = "rx";
378 compatible = "fsl,imx35-spdif";
391 clock-names = "core", "rxtx0",
397 dma-names = "rx", "tx";
402 compatible = "fsl,imx8mn-sai", "fsl,imx8mq-sai";
404 #sound-dai-cells = <0>;
410 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
412 dma-names = "rx", "tx";
417 compatible = "fsl,imx8mn-easrc";
421 clock-names = "mem";
426 dma-names = "ctx0_rx", "ctx0_tx",
430 firmware-name = "imx/easrc/easrc-imx8mn.bin";
431 fsl,asrc-rate = <8000>;
432 fsl,asrc-format = <2>;
438 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
443 gpio-controller;
444 #gpio-cells = <2>;
445 interrupt-controller;
446 #interrupt-cells = <2>;
447 gpio-ranges = <&iomuxc 0 10 30>;
451 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
456 gpio-controller;
457 #gpio-cells = <2>;
458 interrupt-controller;
459 #interrupt-cells = <2>;
460 gpio-ranges = <&iomuxc 0 40 21>;
464 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
469 gpio-controller;
470 #gpio-cells = <2>;
471 interrupt-controller;
472 #interrupt-cells = <2>;
473 gpio-ranges = <&iomuxc 0 61 26>;
477 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
482 gpio-controller;
483 #gpio-cells = <2>;
484 interrupt-controller;
485 #interrupt-cells = <2>;
486 gpio-ranges = <&iomuxc 21 108 11>;
490 compatible = "fsl,imx8mn-gpio", "fsl,imx35-gpio";
495 gpio-controller;
496 #gpio-cells = <2>;
497 interrupt-controller;
498 #interrupt-cells = <2>;
499 gpio-ranges = <&iomuxc 0 119 30>;
503 compatible = "fsl,imx8mn-tmu", "fsl,imx8mm-tmu";
506 nvmem-cells = <&tmu_calib>;
507 nvmem-cell-names = "calib";
508 #thermal-sensor-cells = <0>;
512 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
520 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
528 compatible = "fsl,imx8mn-wdt", "fsl,imx21-wdt";
535 sdma3: dma-controller@302b0000 {
536 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
541 clock-names = "ipg", "ahb";
542 #dma-cells = <3>;
543 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
546 sdma2: dma-controller@302c0000 {
547 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
552 clock-names = "ipg", "ahb";
553 #dma-cells = <3>;
554 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
558 compatible = "fsl,imx8mn-iomuxc";
563 compatible = "fsl,imx8mn-iomuxc-gpr", "syscon";
568 compatible = "fsl,imx8mn-ocotp", "fsl,imx8mm-ocotp", "syscon";
571 #address-cells = <1>;
572 #size-cells = <1>;
587 imx8mn_uid: unique-id@4 { /* 0x410-0x420 */
591 cpu_speed_grade: speed-grade@10 { /* 0x440 */
599 fec_mac_address: mac-address@90 { /* 0x640 */
604 anatop: clock-controller@30360000 {
605 compatible = "fsl,imx8mn-anatop", "fsl,imx8mm-anatop";
607 #clock-cells = <1>;
611 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
614 snvs_rtc: snvs-rtc-lp {
615 compatible = "fsl,sec-v4.0-mon-rtc-lp";
621 clock-names = "snvs-rtc";
624 snvs_pwrkey: snvs-powerkey {
625 compatible = "fsl,sec-v4.0-pwrkey";
629 clock-names = "snvs-pwrkey";
631 wakeup-source;
636 clk: clock-controller@30380000 {
637 compatible = "fsl,imx8mn-ccm";
639 #clock-cells = <1>;
642 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
644 assigned-clocks = <&clk IMX8MN_CLK_A53_SRC>,
652 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_800M>,
656 assigned-clock-rates = <0>, <0>, <0>,
664 src: reset-controller@30390000 {
665 compatible = "fsl,imx8mn-src", "fsl,imx8mq-src", "syscon";
668 #reset-cells = <1>;
672 compatible = "fsl,imx8mn-gpc";
674 interrupt-parent = <&gic>;
678 #address-cells = <1>;
679 #size-cells = <0>;
681 pgc_hsiomix: power-domain@0 {
682 #power-domain-cells = <0>;
687 pgc_otg1: power-domain@1 {
688 #power-domain-cells = <0>;
692 pgc_gpumix: power-domain@2 {
693 #power-domain-cells = <0>;
701 pgc_dispmix: power-domain@3 {
702 #power-domain-cells = <0>;
708 pgc_mipi: power-domain@4 {
709 #power-domain-cells = <0>;
711 power-domains = <&pgc_dispmix>;
718 compatible = "fsl,aips-bus", "simple-bus";
720 #address-cells = <1>;
721 #size-cells = <1>;
725 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
730 clock-names = "ipg", "per";
731 #pwm-cells = <3>;
736 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
741 clock-names = "ipg", "per";
742 #pwm-cells = <3>;
747 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
752 clock-names = "ipg", "per";
753 #pwm-cells = <3>;
758 compatible = "fsl,imx8mn-pwm", "fsl,imx27-pwm";
763 clock-names = "ipg", "per";
764 #pwm-cells = <3>;
769 compatible = "nxp,sysctr-timer";
773 clock-names = "per";
778 compatible = "fsl,aips-bus", "simple-bus";
780 #address-cells = <1>;
781 #size-cells = <1>;
784 spba1: spba-bus@30800000 {
785 compatible = "fsl,spba-bus", "simple-bus";
786 #address-cells = <1>;
787 #size-cells = <1>;
792 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
793 #address-cells = <1>;
794 #size-cells = <0>;
799 clock-names = "ipg", "per";
801 dma-names = "rx", "tx";
806 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
807 #address-cells = <1>;
808 #size-cells = <0>;
813 clock-names = "ipg", "per";
815 dma-names = "rx", "tx";
820 compatible = "fsl,imx8mn-ecspi", "fsl,imx51-ecspi";
821 #address-cells = <1>;
822 #size-cells = <0>;
827 clock-names = "ipg", "per";
829 dma-names = "rx", "tx";
834 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
839 clock-names = "ipg", "per";
841 dma-names = "rx", "tx";
846 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
851 clock-names = "ipg", "per";
853 dma-names = "rx", "tx";
858 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
863 clock-names = "ipg", "per";
869 compatible = "fsl,sec-v4.0";
870 #address-cells = <1>;
871 #size-cells = <1>;
877 clock-names = "aclk", "ipg";
880 compatible = "fsl,sec-v4.0-job-ring";
887 compatible = "fsl,sec-v4.0-job-ring";
893 compatible = "fsl,sec-v4.0-job-ring";
900 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
901 #address-cells = <1>;
902 #size-cells = <0>;
910 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
911 #address-cells = <1>;
912 #size-cells = <0>;
920 #address-cells = <1>;
921 #size-cells = <0>;
922 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
930 compatible = "fsl,imx8mn-i2c", "fsl,imx21-i2c";
931 #address-cells = <1>;
932 #size-cells = <0>;
940 compatible = "fsl,imx8mn-uart", "fsl,imx6q-uart";
945 clock-names = "ipg", "per";
947 dma-names = "rx", "tx";
952 compatible = "fsl,imx8mn-mu", "fsl,imx6sx-mu";
956 #mbox-cells = <2>;
960 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
966 clock-names = "ipg", "ahb", "per";
967 fsl,tuning-start-tap = <20>;
968 fsl,tuning-step = <2>;
969 bus-width = <4>;
974 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
980 clock-names = "ipg", "ahb", "per";
981 fsl,tuning-start-tap = <20>;
982 fsl,tuning-step = <2>;
983 bus-width = <4>;
988 compatible = "fsl,imx8mn-usdhc", "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
994 clock-names = "ipg", "ahb", "per";
995 fsl,tuning-start-tap = <20>;
996 fsl,tuning-step = <2>;
997 bus-width = <4>;
1002 #address-cells = <1>;
1003 #size-cells = <0>;
1004 compatible = "nxp,imx8mm-fspi";
1006 reg-names = "fspi_base", "fspi_mmap";
1010 clock-names = "fspi_en", "fspi";
1014 sdma1: dma-controller@30bd0000 {
1015 compatible = "fsl,imx8mn-sdma", "fsl,imx8mq-sdma";
1020 clock-names = "ipg", "ahb";
1021 #dma-cells = <3>;
1022 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1026 compatible = "fsl,imx8mn-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1037 clock-names = "ipg", "ahb", "ptp",
1039 assigned-clocks = <&clk IMX8MN_CLK_ENET_AXI>,
1043 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1047 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1048 fsl,num-tx-queues = <3>;
1049 fsl,num-rx-queues = <3>;
1050 nvmem-cells = <&fec_mac_address>;
1051 nvmem-cell-names = "mac-address";
1052 fsl,stop-mode = <&gpr 0x10 3>;
1059 compatible = "fsl,aips-bus", "simple-bus";
1061 #address-cells = <1>;
1062 #size-cells = <1>;
1066 compatible = "fsl,imx8mn-lcdif", "fsl,imx6sx-lcdif";
1071 clock-names = "pix", "axi", "disp_axi";
1073 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_LCDIF>;
1078 remote-endpoint = <&dsim_from_lcdif>;
1084 compatible = "fsl,imx8mn-mipi-dsim", "fsl,imx8mm-mipi-dsim";
1088 clock-names = "bus_clk", "sclk_mipi";
1090 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_DSI>;
1094 #address-cells = <1>;
1095 #size-cells = <0>;
1101 remote-endpoint = <&lcdif_to_dsim>;
1108 compatible = "fsl,imx8mn-isi";
1113 clock-names = "axi", "apb";
1114 fsl,blk-ctrl = <&disp_blk_ctrl>;
1115 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_ISI>;
1119 #address-cells = <1>;
1120 #size-cells = <0>;
1125 remote-endpoint = <&mipi_csi_out>;
1131 disp_blk_ctrl: blk-ctrl@32e28000 {
1132 compatible = "fsl,imx8mn-disp-blk-ctrl", "syscon";
1134 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1137 power-domain-names = "bus", "isi",
1138 "lcdif", "mipi-dsi",
1139 "mipi-csi";
1151 clock-names = "disp_axi", "disp_apb",
1153 "lcdif-axi", "lcdif-apb", "lcdif-pix",
1154 "dsi-pclk", "dsi-ref",
1155 "csi-aclk", "csi-pclk";
1156 assigned-clocks = <&clk IMX8MN_CLK_DSI_CORE>,
1161 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_266M>,
1166 assigned-clock-rates = <266000000>,
1171 #power-domain-cells = <1>;
1174 mipi_csi: mipi-csi@32e30000 {
1175 compatible = "fsl,imx8mm-mipi-csi2";
1178 assigned-clocks = <&clk IMX8MN_CLK_CAMERA_PIXEL>;
1179 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>;
1180 assigned-clock-rates = <333000000>;
1181 clock-frequency = <333000000>;
1186 clock-names = "pclk", "wrap", "phy", "axi";
1187 power-domains = <&disp_blk_ctrl IMX8MN_DISPBLK_PD_MIPI_CSI>;
1191 #address-cells = <1>;
1192 #size-cells = <0>;
1202 remote-endpoint = <&isi_in>;
1209 compatible = "fsl,imx8mn-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1213 clock-names = "usb1_ctrl_root_clk";
1214 assigned-clocks = <&clk IMX8MN_CLK_USB_BUS>;
1215 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_500M>;
1218 power-domains = <&pgc_hsiomix>;
1223 compatible = "fsl,imx8mn-usbmisc", "fsl,imx7d-usbmisc",
1224 "fsl,imx6q-usbmisc";
1225 #index-cells = <1>;
1230 dma_apbh: dma-controller@33000000 {
1231 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1237 #dma-cells = <1>;
1238 dma-channels = <4>;
1242 gpmi: nand-controller@33002000 {
1243 compatible = "fsl,imx8mn-gpmi-nand", "fsl,imx7d-gpmi-nand";
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1247 reg-names = "gpmi-nand", "bch";
1249 interrupt-names = "bch";
1252 clock-names = "gpmi_io", "gpmi_bch_apb";
1254 dma-names = "rx-tx";
1266 clock-names = "reg", "bus", "core", "shader";
1267 assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>,
1272 assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>,
1276 assigned-clock-rates = <400000000>,
1281 power-domains = <&pgc_gpumix>;
1284 gic: interrupt-controller@38800000 {
1285 compatible = "arm,gic-v3";
1288 #interrupt-cells = <3>;
1289 interrupt-controller;
1293 ddrc: memory-controller@3d400000 {
1294 compatible = "fsl,imx8mn-ddrc", "fsl,imx8m-ddrc";
1296 clock-names = "core", "pll", "alt", "apb";
1303 ddr-pmu@3d800000 {
1304 compatible = "fsl,imx8mn-ddr-pmu", "fsl,imx8m-ddr-pmu";
1311 #phy-cells = <0>;
1312 compatible = "usb-nop-xceiv";
1314 assigned-clocks = <&clk IMX8MN_CLK_USB_PHY_REF>;
1315 assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_100M>;
1316 clock-names = "main_clk";
1317 power-domains = <&pgc_otg1>;