Lines Matching +full:imx8mq +full:- +full:pcie
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 #include <dt-bindings/clock/imx8mm-clock.h>
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/imx8mm-power.h>
11 #include <dt-bindings/reset/imx8mq-reset.h>
12 #include <dt-bindings/thermal/thermal.h>
14 #include "imx8mm-pinfunc.h"
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
45 #address-cells = <1>;
46 #size-cells = <0>;
48 idle-states {
49 entry-method = "psci";
51 cpu_pd_wait: cpu-pd-wait {
52 compatible = "arm,idle-state";
53 arm,psci-suspend-param = <0x0010033>;
54 local-timer-stop;
55 entry-latency-us = <1000>;
56 exit-latency-us = <700>;
57 min-residency-us = <2700>;
63 compatible = "arm,cortex-a53";
65 clock-latency = <61036>; /* two CLK32 periods */
67 enable-method = "psci";
68 i-cache-size = <0x8000>;
69 i-cache-line-size = <64>;
70 i-cache-sets = <256>;
71 d-cache-size = <0x8000>;
72 d-cache-line-size = <64>;
73 d-cache-sets = <128>;
74 next-level-cache = <&A53_L2>;
75 operating-points-v2 = <&a53_opp_table>;
76 nvmem-cells = <&cpu_speed_grade>;
77 nvmem-cell-names = "speed_grade";
78 cpu-idle-states = <&cpu_pd_wait>;
79 #cooling-cells = <2>;
84 compatible = "arm,cortex-a53";
86 clock-latency = <61036>; /* two CLK32 periods */
88 enable-method = "psci";
89 i-cache-size = <0x8000>;
90 i-cache-line-size = <64>;
91 i-cache-sets = <256>;
92 d-cache-size = <0x8000>;
93 d-cache-line-size = <64>;
94 d-cache-sets = <128>;
95 next-level-cache = <&A53_L2>;
96 operating-points-v2 = <&a53_opp_table>;
97 cpu-idle-states = <&cpu_pd_wait>;
98 #cooling-cells = <2>;
103 compatible = "arm,cortex-a53";
105 clock-latency = <61036>; /* two CLK32 periods */
107 enable-method = "psci";
108 i-cache-size = <0x8000>;
109 i-cache-line-size = <64>;
110 i-cache-sets = <256>;
111 d-cache-size = <0x8000>;
112 d-cache-line-size = <64>;
113 d-cache-sets = <128>;
114 next-level-cache = <&A53_L2>;
115 operating-points-v2 = <&a53_opp_table>;
116 cpu-idle-states = <&cpu_pd_wait>;
117 #cooling-cells = <2>;
122 compatible = "arm,cortex-a53";
124 clock-latency = <61036>; /* two CLK32 periods */
126 enable-method = "psci";
127 i-cache-size = <0x8000>;
128 i-cache-line-size = <64>;
129 i-cache-sets = <256>;
130 d-cache-size = <0x8000>;
131 d-cache-line-size = <64>;
132 d-cache-sets = <128>;
133 next-level-cache = <&A53_L2>;
134 operating-points-v2 = <&a53_opp_table>;
135 cpu-idle-states = <&cpu_pd_wait>;
136 #cooling-cells = <2>;
139 A53_L2: l2-cache0 {
141 cache-level = <2>;
142 cache-unified;
143 cache-size = <0x80000>;
144 cache-line-size = <64>;
145 cache-sets = <512>;
149 a53_opp_table: opp-table {
150 compatible = "operating-points-v2";
151 opp-shared;
153 opp-1200000000 {
154 opp-hz = /bits/ 64 <1200000000>;
155 opp-microvolt = <850000>;
156 opp-supported-hw = <0xe>, <0x7>;
157 clock-latency-ns = <150000>;
158 opp-suspend;
161 opp-1600000000 {
162 opp-hz = /bits/ 64 <1600000000>;
163 opp-microvolt = <950000>;
164 opp-supported-hw = <0xc>, <0x7>;
165 clock-latency-ns = <150000>;
166 opp-suspend;
169 opp-1800000000 {
170 opp-hz = /bits/ 64 <1800000000>;
171 opp-microvolt = <1000000>;
172 opp-supported-hw = <0x8>, <0x3>;
173 clock-latency-ns = <150000>;
174 opp-suspend;
178 osc_32k: clock-osc-32k {
179 compatible = "fixed-clock";
180 #clock-cells = <0>;
181 clock-frequency = <32768>;
182 clock-output-names = "osc_32k";
185 osc_24m: clock-osc-24m {
186 compatible = "fixed-clock";
187 #clock-cells = <0>;
188 clock-frequency = <24000000>;
189 clock-output-names = "osc_24m";
192 clk_ext1: clock-ext1 {
193 compatible = "fixed-clock";
194 #clock-cells = <0>;
195 clock-frequency = <133000000>;
196 clock-output-names = "clk_ext1";
199 clk_ext2: clock-ext2 {
200 compatible = "fixed-clock";
201 #clock-cells = <0>;
202 clock-frequency = <133000000>;
203 clock-output-names = "clk_ext2";
206 clk_ext3: clock-ext3 {
207 compatible = "fixed-clock";
208 #clock-cells = <0>;
209 clock-frequency = <133000000>;
210 clock-output-names = "clk_ext3";
213 clk_ext4: clock-ext4 {
214 compatible = "fixed-clock";
215 #clock-cells = <0>;
216 clock-frequency = <133000000>;
217 clock-output-names = "clk_ext4";
221 compatible = "arm,psci-1.0";
226 compatible = "arm,cortex-a53-pmu";
232 compatible = "arm,armv8-timer";
234 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, /* Physical Non-Secure */
237 clock-frequency = <8000000>;
238 arm,no-tick-in-suspend;
241 thermal-zones {
242 cpu-thermal {
243 polling-delay-passive = <250>;
244 polling-delay = <2000>;
245 thermal-sensors = <&tmu>;
260 cooling-maps {
263 cooling-device =
274 #phy-cells = <0>;
275 compatible = "usb-nop-xceiv";
277 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
278 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
279 clock-names = "main_clk";
280 power-domains = <&pgc_otg1>;
284 #phy-cells = <0>;
285 compatible = "usb-nop-xceiv";
287 assigned-clocks = <&clk IMX8MM_CLK_USB_PHY_REF>;
288 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_100M>;
289 clock-names = "main_clk";
290 power-domains = <&pgc_otg2>;
294 compatible = "fsl,imx8mm-soc", "simple-bus";
295 #address-cells = <1>;
296 #size-cells = <1>;
298 dma-ranges = <0x40000000 0x0 0x40000000 0xc0000000>;
299 nvmem-cells = <&imx8mm_uid>;
300 nvmem-cell-names = "soc_unique_id";
303 compatible = "fsl,aips-bus", "simple-bus";
305 #address-cells = <1>;
306 #size-cells = <1>;
309 spba2: spba-bus@30000000 {
310 compatible = "fsl,spba-bus", "simple-bus";
311 #address-cells = <1>;
312 #size-cells = <1>;
317 #sound-dai-cells = <0>;
318 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
324 clock-names = "bus", "mclk1", "mclk2", "mclk3";
326 dma-names = "rx", "tx";
331 #sound-dai-cells = <0>;
332 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
338 clock-names = "bus", "mclk1", "mclk2", "mclk3";
340 dma-names = "rx", "tx";
345 #sound-dai-cells = <0>;
346 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
352 clock-names = "bus", "mclk1", "mclk2", "mclk3";
354 dma-names = "rx", "tx";
359 #sound-dai-cells = <0>;
360 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
366 clock-names = "bus", "mclk1", "mclk2", "mclk3";
368 dma-names = "rx", "tx";
373 #sound-dai-cells = <0>;
374 compatible = "fsl,imx8mm-sai", "fsl,imx8mq-sai";
380 clock-names = "bus", "mclk1", "mclk2", "mclk3";
382 dma-names = "rx", "tx";
386 micfil: audio-controller@30080000 {
387 compatible = "fsl,imx8mm-micfil";
398 clock-names = "ipg_clk", "ipg_clk_app",
401 dma-names = "rx";
406 compatible = "fsl,imx35-spdif";
419 clock-names = "core", "rxtx0",
425 dma-names = "rx", "tx";
431 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
436 gpio-controller;
437 #gpio-cells = <2>;
438 interrupt-controller;
439 #interrupt-cells = <2>;
440 gpio-ranges = <&iomuxc 0 10 30>;
444 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
449 gpio-controller;
450 #gpio-cells = <2>;
451 interrupt-controller;
452 #interrupt-cells = <2>;
453 gpio-ranges = <&iomuxc 0 40 21>;
457 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
462 gpio-controller;
463 #gpio-cells = <2>;
464 interrupt-controller;
465 #interrupt-cells = <2>;
466 gpio-ranges = <&iomuxc 0 61 26>;
470 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
475 gpio-controller;
476 #gpio-cells = <2>;
477 interrupt-controller;
478 #interrupt-cells = <2>;
479 gpio-ranges = <&iomuxc 0 87 32>;
483 compatible = "fsl,imx8mm-gpio", "fsl,imx35-gpio";
488 gpio-controller;
489 #gpio-cells = <2>;
490 interrupt-controller;
491 #interrupt-cells = <2>;
492 gpio-ranges = <&iomuxc 0 119 30>;
496 compatible = "fsl,imx8mm-tmu";
499 nvmem-cells = <&tmu_calib>;
500 nvmem-cell-names = "calib";
501 #thermal-sensor-cells = <0>;
505 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
513 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
521 compatible = "fsl,imx8mm-wdt", "fsl,imx21-wdt";
528 sdma2: dma-controller@302c0000 {
529 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
534 clock-names = "ipg", "ahb";
535 #dma-cells = <3>;
536 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
539 sdma3: dma-controller@302b0000 {
540 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
545 clock-names = "ipg", "ahb";
546 #dma-cells = <3>;
547 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
551 compatible = "fsl,imx8mm-iomuxc";
556 compatible = "fsl,imx8mm-iomuxc-gpr", "syscon";
561 compatible = "fsl,imx8mm-ocotp", "syscon";
565 #address-cells = <1>;
566 #size-cells = <1>;
581 imx8mm_uid: unique-id@4 { /* 0x410-0x420 */
585 cpu_speed_grade: speed-grade@10 { /* 0x440 */
593 fec_mac_address: mac-address@90 { /* 0x640 */
598 anatop: clock-controller@30360000 {
599 compatible = "fsl,imx8mm-anatop";
601 #clock-cells = <1>;
605 compatible = "fsl,sec-v4.0-mon","syscon", "simple-mfd";
608 snvs_rtc: snvs-rtc-lp {
609 compatible = "fsl,sec-v4.0-mon-rtc-lp";
615 clock-names = "snvs-rtc";
618 snvs_pwrkey: snvs-powerkey {
619 compatible = "fsl,sec-v4.0-pwrkey";
623 clock-names = "snvs-pwrkey";
625 wakeup-source;
629 snvs_lpgpr: snvs-lpgpr {
630 compatible = "fsl,imx8mm-snvs-lpgpr",
631 "fsl,imx7d-snvs-lpgpr";
635 clk: clock-controller@30380000 {
636 compatible = "fsl,imx8mm-ccm";
638 #clock-cells = <1>;
641 clock-names = "osc_32k", "osc_24m", "clk_ext1", "clk_ext2",
643 assigned-clocks = <&clk IMX8MM_CLK_A53_SRC>,
651 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
655 assigned-clock-rates = <0>, <0>, <0>,
663 src: reset-controller@30390000 {
664 compatible = "fsl,imx8mm-src", "fsl,imx8mq-src", "syscon";
667 #reset-cells = <1>;
671 compatible = "fsl,imx8mm-gpc";
674 interrupt-parent = <&gic>;
675 interrupt-controller;
676 #interrupt-cells = <3>;
679 #address-cells = <1>;
680 #size-cells = <0>;
682 pgc_hsiomix: power-domain@0 {
683 #power-domain-cells = <0>;
686 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
687 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
690 pgc_pcie: power-domain@1 {
691 #power-domain-cells = <0>;
693 power-domains = <&pgc_hsiomix>;
697 pgc_otg1: power-domain@2 {
698 #power-domain-cells = <0>;
702 pgc_otg2: power-domain@3 {
703 #power-domain-cells = <0>;
707 pgc_gpumix: power-domain@4 {
708 #power-domain-cells = <0>;
712 assigned-clocks = <&clk IMX8MM_CLK_GPU_AXI>,
714 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>,
716 assigned-clock-rates = <800000000>, <400000000>;
719 pgc_gpu: power-domain@5 {
720 #power-domain-cells = <0>;
727 power-domains = <&pgc_gpumix>;
730 pgc_vpumix: power-domain@6 {
731 #power-domain-cells = <0>;
734 assigned-clocks = <&clk IMX8MM_CLK_VPU_BUS>;
735 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>;
738 pgc_vpu_g1: power-domain@7 {
739 #power-domain-cells = <0>;
743 pgc_vpu_g2: power-domain@8 {
744 #power-domain-cells = <0>;
748 pgc_vpu_h1: power-domain@9 {
749 #power-domain-cells = <0>;
753 pgc_dispmix: power-domain@10 {
754 #power-domain-cells = <0>;
758 assigned-clocks = <&clk IMX8MM_CLK_DISP_AXI>,
760 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>,
762 assigned-clock-rates = <500000000>, <200000000>;
765 pgc_mipi: power-domain@11 {
766 #power-domain-cells = <0>;
774 compatible = "fsl,aips-bus", "simple-bus";
776 #address-cells = <1>;
777 #size-cells = <1>;
781 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
786 clock-names = "ipg", "per";
787 #pwm-cells = <3>;
792 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
797 clock-names = "ipg", "per";
798 #pwm-cells = <3>;
803 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
808 clock-names = "ipg", "per";
809 #pwm-cells = <3>;
814 compatible = "fsl,imx8mm-pwm", "fsl,imx27-pwm";
819 clock-names = "ipg", "per";
820 #pwm-cells = <3>;
825 compatible = "nxp,sysctr-timer";
829 clock-names = "per";
834 compatible = "fsl,aips-bus", "simple-bus";
836 #address-cells = <1>;
837 #size-cells = <1>;
841 spba1: spba-bus@30800000 {
842 compatible = "fsl,spba-bus", "simple-bus";
843 #address-cells = <1>;
844 #size-cells = <1>;
849 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
850 #address-cells = <1>;
851 #size-cells = <0>;
856 clock-names = "ipg", "per";
858 dma-names = "rx", "tx";
863 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
864 #address-cells = <1>;
865 #size-cells = <0>;
870 clock-names = "ipg", "per";
872 dma-names = "rx", "tx";
877 compatible = "fsl,imx8mm-ecspi", "fsl,imx51-ecspi";
878 #address-cells = <1>;
879 #size-cells = <0>;
884 clock-names = "ipg", "per";
886 dma-names = "rx", "tx";
891 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
896 clock-names = "ipg", "per";
898 dma-names = "rx", "tx";
903 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
908 clock-names = "ipg", "per";
910 dma-names = "rx", "tx";
915 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
920 clock-names = "ipg", "per";
926 compatible = "fsl,sec-v4.0";
927 #address-cells = <1>;
928 #size-cells = <1>;
934 clock-names = "aclk", "ipg";
937 compatible = "fsl,sec-v4.0-job-ring";
944 compatible = "fsl,sec-v4.0-job-ring";
950 compatible = "fsl,sec-v4.0-job-ring";
957 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
958 #address-cells = <1>;
959 #size-cells = <0>;
967 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
968 #address-cells = <1>;
969 #size-cells = <0>;
977 #address-cells = <1>;
978 #size-cells = <0>;
979 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
987 compatible = "fsl,imx8mm-i2c", "fsl,imx21-i2c";
988 #address-cells = <1>;
989 #size-cells = <0>;
997 compatible = "fsl,imx8mm-uart", "fsl,imx6q-uart";
1002 clock-names = "ipg", "per";
1004 dma-names = "rx", "tx";
1009 compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
1013 #mbox-cells = <2>;
1017 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1023 clock-names = "ipg", "ahb", "per";
1024 fsl,tuning-start-tap = <20>;
1025 fsl,tuning-step = <2>;
1026 bus-width = <4>;
1031 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1037 clock-names = "ipg", "ahb", "per";
1038 fsl,tuning-start-tap = <20>;
1039 fsl,tuning-step = <2>;
1040 bus-width = <4>;
1045 compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
1051 clock-names = "ipg", "ahb", "per";
1052 fsl,tuning-start-tap = <20>;
1053 fsl,tuning-step = <2>;
1054 bus-width = <4>;
1059 #address-cells = <1>;
1060 #size-cells = <0>;
1061 compatible = "nxp,imx8mm-fspi";
1063 reg-names = "fspi_base", "fspi_mmap";
1067 clock-names = "fspi_en", "fspi";
1071 sdma1: dma-controller@30bd0000 {
1072 compatible = "fsl,imx8mm-sdma", "fsl,imx8mq-sdma";
1077 clock-names = "ipg", "ahb";
1078 #dma-cells = <3>;
1079 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx7d.bin";
1083 compatible = "fsl,imx8mm-fec", "fsl,imx8mq-fec", "fsl,imx6sx-fec";
1094 clock-names = "ipg", "ahb", "ptp",
1096 assigned-clocks = <&clk IMX8MM_CLK_ENET_AXI>,
1100 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1104 assigned-clock-rates = <0>, <100000000>, <125000000>, <0>;
1105 fsl,num-tx-queues = <3>;
1106 fsl,num-rx-queues = <3>;
1107 nvmem-cells = <&fec_mac_address>;
1108 nvmem-cell-names = "mac-address";
1109 fsl,stop-mode = <&gpr 0x10 3>;
1116 compatible = "fsl,aips-bus", "simple-bus";
1118 #address-cells = <1>;
1119 #size-cells = <1>;
1123 compatible = "fsl,imx8mm-lcdif", "fsl,imx6sx-lcdif";
1128 clock-names = "pix", "axi", "disp_axi";
1129 assigned-clocks = <&clk IMX8MM_CLK_LCDIF_PIXEL>,
1132 assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>,
1135 assigned-clock-rates = <594000000>, <500000000>, <200000000>;
1137 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>;
1142 remote-endpoint = <&dsim_from_lcdif>;
1148 compatible = "fsl,imx8mm-mipi-dsim";
1152 clock-names = "bus_clk", "sclk_mipi";
1153 assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>,
1155 assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>,
1157 assigned-clock-rates = <266000000>, <24000000>;
1158 samsung,pll-clock-frequency = <24000000>;
1160 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>;
1164 #address-cells = <1>;
1165 #size-cells = <0>;
1171 remote-endpoint = <&lcdif_to_dsim>;
1178 compatible = "fsl,imx8mm-csi", "fsl,imx7-csi";
1182 clock-names = "mclk";
1183 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_CSI_BRIDGE>;
1188 remote-endpoint = <&imx8mm_mipi_csi_out>;
1193 disp_blk_ctrl: blk-ctrl@32e28000 {
1194 compatible = "fsl,imx8mm-disp-blk-ctrl", "syscon";
1196 power-domains = <&pgc_dispmix>, <&pgc_dispmix>,
1199 power-domain-names = "bus", "csi-bridge",
1200 "lcdif", "mipi-dsi",
1201 "mipi-csi";
1212 clock-names = "csi-bridge-axi","csi-bridge-apb",
1213 "csi-bridge-core", "lcdif-axi",
1214 "lcdif-apb", "lcdif-pix",
1215 "dsi-pclk", "dsi-ref",
1216 "csi-aclk", "csi-pclk";
1217 #power-domain-cells = <1>;
1220 mipi_csi: mipi-csi@32e30000 {
1221 compatible = "fsl,imx8mm-mipi-csi2";
1224 assigned-clocks = <&clk IMX8MM_CLK_CSI1_CORE>;
1225 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_1000M>;
1227 clock-frequency = <333000000>;
1232 clock-names = "pclk", "wrap", "phy", "axi";
1233 power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_CSI>;
1237 #address-cells = <1>;
1238 #size-cells = <0>;
1248 remote-endpoint = <&csi_in>;
1255 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1259 clock-names = "usb1_ctrl_root_clk";
1260 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1261 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1264 power-domains = <&pgc_hsiomix>;
1269 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1270 "fsl,imx6q-usbmisc";
1271 #index-cells = <1>;
1276 compatible = "fsl,imx8mm-usb", "fsl,imx7d-usb", "fsl,imx27-usb";
1280 clock-names = "usb1_ctrl_root_clk";
1281 assigned-clocks = <&clk IMX8MM_CLK_USB_BUS>;
1282 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_500M>;
1285 power-domains = <&pgc_hsiomix>;
1290 compatible = "fsl,imx8mm-usbmisc", "fsl,imx7d-usbmisc",
1291 "fsl,imx6q-usbmisc";
1292 #index-cells = <1>;
1296 pcie_phy: pcie-phy@32f00000 {
1297 compatible = "fsl,imx8mm-pcie-phy";
1300 clock-names = "ref";
1301 assigned-clocks = <&clk IMX8MM_CLK_PCIE1_PHY>;
1302 assigned-clock-rates = <100000000>;
1303 assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_100M>;
1305 reset-names = "pciephy";
1306 #phy-cells = <0>;
1311 dma_apbh: dma-controller@33000000 {
1312 compatible = "fsl,imx7d-dma-apbh", "fsl,imx28-dma-apbh";
1318 #dma-cells = <1>;
1319 dma-channels = <4>;
1323 gpmi: nand-controller@33002000 {
1324 compatible = "fsl,imx8mm-gpmi-nand", "fsl,imx7d-gpmi-nand";
1325 #address-cells = <1>;
1326 #size-cells = <0>;
1328 reg-names = "gpmi-nand", "bch";
1330 interrupt-names = "bch";
1333 clock-names = "gpmi_io", "gpmi_bch_apb";
1335 dma-names = "rx-tx";
1339 pcie0: pcie@33800000 {
1340 compatible = "fsl,imx8mm-pcie";
1342 reg-names = "dbi", "config";
1343 #address-cells = <3>;
1344 #size-cells = <2>;
1346 bus-range = <0x00 0xff>;
1348 <0x82000000 0 0x18000000 0x18000000 0 0x07f00000>; /* non-prefetchable memory */
1349 num-lanes = <1>;
1350 num-viewport = <4>;
1352 interrupt-names = "msi";
1353 #interrupt-cells = <1>;
1354 interrupt-map-mask = <0 0 0 0x7>;
1355 interrupt-map = <0 0 0 1 &gic GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
1359 fsl,max-link-speed = <2>;
1360 linux,pci-domain = <0>;
1364 clock-names = "pcie", "pcie_bus", "pcie_aux";
1365 power-domains = <&pgc_pcie>;
1368 reset-names = "apps", "turnoff";
1370 phy-names = "pcie-phy";
1374 pcie0_ep: pcie-ep@33800000 {
1375 compatible = "fsl,imx8mm-pcie-ep";
1378 reg-names = "dbi", "addr_space";
1379 num-lanes = <1>;
1381 interrupt-names = "dma";
1382 fsl,max-link-speed = <2>;
1386 clock-names = "pcie", "pcie_bus", "pcie_aux";
1387 power-domains = <&pgc_pcie>;
1390 reset-names = "apps", "turnoff";
1392 phy-names = "pcie-phy";
1393 num-ib-windows = <4>;
1394 num-ob-windows = <4>;
1406 clock-names = "reg", "bus", "core", "shader";
1407 assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>,
1409 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1410 assigned-clock-rates = <0>, <1000000000>;
1411 power-domains = <&pgc_gpu>;
1421 clock-names = "reg", "bus", "core";
1422 assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>,
1424 assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>;
1425 assigned-clock-rates = <0>, <1000000000>;
1426 power-domains = <&pgc_gpu>;
1429 vpu_g1: video-codec@38300000 {
1430 compatible = "nxp,imx8mm-vpu-g1";
1434 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G1>;
1437 vpu_g2: video-codec@38310000 {
1438 compatible = "nxp,imx8mq-vpu-g2";
1442 power-domains = <&vpu_blk_ctrl IMX8MM_VPUBLK_PD_G2>;
1445 vpu_blk_ctrl: blk-ctrl@38330000 {
1446 compatible = "fsl,imx8mm-vpu-blk-ctrl", "syscon";
1448 power-domains = <&pgc_vpumix>, <&pgc_vpu_g1>,
1450 power-domain-names = "bus", "g1", "g2", "h1";
1454 clock-names = "g1", "g2", "h1";
1455 assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>,
1457 assigned-clock-parents = <&clk IMX8MM_VPU_PLL_OUT>,
1459 assigned-clock-rates = <600000000>,
1461 #power-domain-cells = <1>;
1464 gic: interrupt-controller@38800000 {
1465 compatible = "arm,gic-v3";
1468 #interrupt-cells = <3>;
1469 interrupt-controller;
1473 ddrc: memory-controller@3d400000 {
1474 compatible = "fsl,imx8mm-ddrc", "fsl,imx8m-ddrc";
1476 clock-names = "core", "pll", "alt", "apb";
1483 ddr-pmu@3d800000 {
1484 compatible = "fsl,imx8mm-ddr-pmu", "fsl,imx8m-ddr-pmu";