Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <dt-bindings/clock/imx8-lpcg.h>
8 #include <dt-bindings/firmware/imx/rsrc.h>
11 compatible = "simple-bus";
12 #address-cells = <1>;
13 #size-cells = <1>;
17 lsio_mem_clk: clock-lsio-mem {
18 compatible = "fixed-clock";
19 #clock-cells = <0>;
20 clock-frequency = <200000000>;
21 clock-output-names = "lsio_mem_clk";
24 lsio_bus_clk: clock-lsio-bus {
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
27 clock-frequency = <100000000>;
28 clock-output-names = "lsio_bus_clk";
32 compatible = "fsl,imx27-pwm";
34 clock-names = "ipg", "per";
37 assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>;
38 assigned-clock-rates = <24000000>;
39 #pwm-cells = <2>;
44 compatible = "fsl,imx27-pwm";
46 clock-names = "ipg", "per";
49 assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>;
50 assigned-clock-rates = <24000000>;
51 #pwm-cells = <2>;
56 compatible = "fsl,imx27-pwm";
58 clock-names = "ipg", "per";
61 assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>;
62 assigned-clock-rates = <24000000>;
63 #pwm-cells = <2>;
68 compatible = "fsl,imx27-pwm";
70 clock-names = "ipg", "per";
73 assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>;
74 assigned-clock-rates = <24000000>;
75 #pwm-cells = <2>;
82 gpio-controller;
83 #gpio-cells = <2>;
84 interrupt-controller;
85 #interrupt-cells = <2>;
86 power-domains = <&pd IMX_SC_R_GPIO_0>;
92 gpio-controller;
93 #gpio-cells = <2>;
94 interrupt-controller;
95 #interrupt-cells = <2>;
96 power-domains = <&pd IMX_SC_R_GPIO_1>;
102 gpio-controller;
103 #gpio-cells = <2>;
104 interrupt-controller;
105 #interrupt-cells = <2>;
106 power-domains = <&pd IMX_SC_R_GPIO_2>;
112 gpio-controller;
113 #gpio-cells = <2>;
114 interrupt-controller;
115 #interrupt-cells = <2>;
116 power-domains = <&pd IMX_SC_R_GPIO_3>;
122 gpio-controller;
123 #gpio-cells = <2>;
124 interrupt-controller;
125 #interrupt-cells = <2>;
126 power-domains = <&pd IMX_SC_R_GPIO_4>;
132 gpio-controller;
133 #gpio-cells = <2>;
134 interrupt-controller;
135 #interrupt-cells = <2>;
136 power-domains = <&pd IMX_SC_R_GPIO_5>;
142 gpio-controller;
143 #gpio-cells = <2>;
144 interrupt-controller;
145 #interrupt-cells = <2>;
146 power-domains = <&pd IMX_SC_R_GPIO_6>;
152 gpio-controller;
153 #gpio-cells = <2>;
154 interrupt-controller;
155 #interrupt-cells = <2>;
156 power-domains = <&pd IMX_SC_R_GPIO_7>;
160 #address-cells = <1>;
161 #size-cells = <0>;
162 compatible = "nxp,imx8qxp-fspi";
164 reg-names = "fspi_base", "fspi_mmap";
168 clock-names = "fspi_en", "fspi";
169 power-domains = <&pd IMX_SC_R_FSPI_0>;
176 #mbox-cells = <2>;
183 #mbox-cells = <2>;
189 #mbox-cells = <2>;
196 #mbox-cells = <2>;
203 #mbox-cells = <2>;
210 #mbox-cells = <2>;
211 power-domains = <&pd IMX_SC_R_MU_5A>;
218 #mbox-cells = <2>;
219 power-domains = <&pd IMX_SC_R_MU_6A>;
226 #mbox-cells = <2>;
227 power-domains = <&pd IMX_SC_R_MU_13A>;
230 /* LPCG clocks */
231 pwm0_lpcg: clock-controller@5d400000 {
232 compatible = "fsl,imx8qxp-lpcg";
234 #clock-cells = <1>;
240 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
243 clock-output-names = "pwm0_lpcg_ipg_clk",
248 power-domains = <&pd IMX_SC_R_PWM_0>;
251 pwm1_lpcg: clock-controller@5d410000 {
252 compatible = "fsl,imx8qxp-lpcg";
254 #clock-cells = <1>;
260 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
263 clock-output-names = "pwm1_lpcg_ipg_clk",
268 power-domains = <&pd IMX_SC_R_PWM_1>;
271 pwm2_lpcg: clock-controller@5d420000 {
272 compatible = "fsl,imx8qxp-lpcg";
274 #clock-cells = <1>;
280 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
283 clock-output-names = "pwm2_lpcg_ipg_clk",
288 power-domains = <&pd IMX_SC_R_PWM_2>;
291 pwm3_lpcg: clock-controller@5d430000 {
292 compatible = "fsl,imx8qxp-lpcg";
294 #clock-cells = <1>;
300 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
303 clock-output-names = "pwm3_lpcg_ipg_clk",
308 power-domains = <&pd IMX_SC_R_PWM_3>;
311 pwm4_lpcg: clock-controller@5d440000 {
312 compatible = "fsl,imx8qxp-lpcg";
314 #clock-cells = <1>;
320 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
323 clock-output-names = "pwm4_lpcg_ipg_clk",
328 power-domains = <&pd IMX_SC_R_PWM_4>;
331 pwm5_lpcg: clock-controller@5d450000 {
332 compatible = "fsl,imx8qxp-lpcg";
334 #clock-cells = <1>;
340 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
343 clock-output-names = "pwm5_lpcg_ipg_clk",
348 power-domains = <&pd IMX_SC_R_PWM_5>;
351 pwm6_lpcg: clock-controller@5d460000 {
352 compatible = "fsl,imx8qxp-lpcg";
354 #clock-cells = <1>;
360 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
363 clock-output-names = "pwm6_lpcg_ipg_clk",
368 power-domains = <&pd IMX_SC_R_PWM_6>;
371 pwm7_lpcg: clock-controller@5d470000 {
372 compatible = "fsl,imx8qxp-lpcg";
374 #clock-cells = <1>;
380 clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
383 clock-output-names = "pwm7_lpcg_ipg_clk",
388 power-domains = <&pd IMX_SC_R_PWM_7>;