Lines Matching +full:imx8qxp +full:- +full:lpcg
1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2019-2021 NXP
7 compatible = "simple-bus";
8 #address-cells = <1>;
9 #size-cells = <1>;
12 img_ipg_clk: clock-img-ipg {
13 compatible = "fixed-clock";
14 #clock-cells = <0>;
15 clock-frequency = <200000000>;
16 clock-output-names = "img_ipg_clk";
27 clock-names = "per", "ipg";
28 assigned-clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
30 assigned-clock-rates = <200000000>, <200000000>;
31 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
46 clock-names = "per", "ipg";
47 assigned-clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
49 assigned-clock-rates = <200000000>, <200000000>;
50 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
57 img_jpeg_dec_lpcg: clock-controller@585d0000 {
58 compatible = "fsl,imx8qxp-lpcg";
60 #clock-cells = <1>;
62 clock-indices = <IMX_LPCG_CLK_0>,
64 clock-output-names = "img_jpeg_dec_lpcg_clk",
66 power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>;
69 img_jpeg_enc_lpcg: clock-controller@585f0000 {
70 compatible = "fsl,imx8qxp-lpcg";
72 #clock-cells = <1>;
74 clock-indices = <IMX_LPCG_CLK_0>,
76 clock-output-names = "img_jpeg_enc_lpcg_clk",
78 power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>;