Lines Matching +full:0 +full:x5a880000
14 ranges = <0x5a000000 0x0 0x5a000000 0x1000000>;
18 #clock-cells = <0>;
25 reg = <0x5a000000 0x10000>;
27 #size-cells = <0>;
30 clocks = <&spi0_lpcg 0>,
41 reg = <0x5a010000 0x10000>;
43 #size-cells = <0>;
46 clocks = <&spi1_lpcg 0>,
57 reg = <0x5a020000 0x10000>;
59 #size-cells = <0>;
62 clocks = <&spi2_lpcg 0>,
73 reg = <0x5a030000 0x10000>;
75 #size-cells = <0>;
78 clocks = <&spi3_lpcg 0>,
88 reg = <0x5a060000 0x1000>;
100 reg = <0x5a070000 0x1000>;
112 reg = <0x5a080000 0x1000>;
124 reg = <0x5a090000 0x1000>;
137 reg = <0x5a400000 0x10000>;
149 reg = <0x5a410000 0x10000>;
161 reg = <0x5a420000 0x10000>;
173 reg = <0x5a430000 0x10000>;
185 reg = <0x5a460000 0x10000>;
197 reg = <0x5a470000 0x10000>;
209 reg = <0x5a480000 0x10000>;
221 reg = <0x5a490000 0x10000>;
232 reg = <0x5a800000 0x4000>;
244 reg = <0x5a810000 0x4000>;
256 reg = <0x5a820000 0x4000>;
268 reg = <0x5a830000 0x4000>;
282 reg = <0x5a880000 0x10000>;
285 clocks = <&adc0_lpcg 0>,
297 reg = <0x5a890000 0x10000>;
300 clocks = <&adc1_lpcg 0>,
311 reg = <0x5a8d0000 0x10000>;
315 <&can0_lpcg 0>;
321 fsl,clk-source = /bits/ 8 <0>;
322 fsl,scu-index = /bits/ 8 <0>;
328 reg = <0x5a8e0000 0x10000>;
336 <&can0_lpcg 0>;
342 fsl,clk-source = /bits/ 8 <0>;
349 reg = <0x5a8f0000 0x10000>;
357 <&can0_lpcg 0>;
363 fsl,clk-source = /bits/ 8 <0>;
370 reg = <0x5ac00000 0x10000>;
382 reg = <0x5ac10000 0x10000>;
394 reg = <0x5ac20000 0x10000>;
406 reg = <0x5ac30000 0x10000>;
418 reg = <0x5ac80000 0x10000>;
430 reg = <0x5ac90000 0x10000>;
442 reg = <0x5acd0000 0x10000>;