Lines Matching +full:0 +full:x11420000
48 #clock-cells = <0>;
53 #size-cells = <0>;
91 reg = <0x100>;
96 i-cache-size = <0x8000>;
99 d-cache-size = <0x8000>;
109 reg = <0x101>;
112 i-cache-size = <0x8000>;
115 d-cache-size = <0x8000>;
125 reg = <0x102>;
128 i-cache-size = <0x8000>;
131 d-cache-size = <0x8000>;
141 reg = <0x103>;
144 i-cache-size = <0x8000>;
147 d-cache-size = <0x8000>;
153 cpu4: cpu@0 {
157 reg = <0x0>;
162 i-cache-size = <0xc000>;
165 d-cache-size = <0x8000>;
175 reg = <0x1>;
178 i-cache-size = <0xc000>;
181 d-cache-size = <0x8000>;
191 reg = <0x2>;
194 i-cache-size = <0xc000>;
197 d-cache-size = <0x8000>;
207 reg = <0x3>;
210 i-cache-size = <0xc000>;
213 d-cache-size = <0x8000>;
223 cache-size = <0x200000>;
232 cache-size = <0x40000>;
238 cluster_a53_opp_table: opp-table-0 {
353 cpu_off = <0x84000002>;
354 cpu_on = <0xc4000003>;
357 soc: soc@0 {
361 ranges = <0x0 0x0 0x0 0x18000000>;
365 reg = <0x10000000 0x100>;
370 reg = <0x10030000 0x1000>;
385 reg = <0x10fc0000 0x1000>;
394 reg = <0x105b0000 0x2000>;
405 reg = <0x14c80000 0x1000>;
411 reg = <0x10040000 0x1000>;
417 reg = <0x156e0000 0x1000>;
444 reg = <0x12460000 0x1000>;
458 reg = <0x13b90000 0x1000>;
484 reg = <0x114c0000 0x1000>;
493 reg = <0x13600000 0x1000>;
502 reg = <0x14800000 0x1000>;
511 reg = <0x13400000 0x1000>;
520 reg = <0x14aa0000 0x2000>;
530 reg = <0x13cf0000 0x1000>;
544 reg = <0x11900000 0x2000>;
553 reg = <0x11800000 0x2000>;
562 reg = <0x150d0000 0x1000>;
576 reg = <0x15280000 0x1000>;
586 reg = <0x14f80000 0x1000>;
596 reg = <0x146d0000 0x1000>;
610 reg = <0x120d0000 0x1000>;
626 reg = <0x145d0000 0x1000>;
648 reg = <0x11060000 0x1000>;
663 reg = <0x11140000 0x1000>;
672 reg = <0x105c4000 0x20>;
673 #power-domain-cells = <0>;
679 reg = <0x105c4020 0x20>;
680 #power-domain-cells = <0>;
687 reg = <0x105c4040 0x20>;
688 #power-domain-cells = <0>;
694 reg = <0x105c4060 0x20>;
695 #power-domain-cells = <0>;
701 reg = <0x105c4080 0x20>;
702 #power-domain-cells = <0>;
708 reg = <0x105c40a0 0x20>;
709 #power-domain-cells = <0>;
715 reg = <0x105c40c0 0x20>;
716 #power-domain-cells = <0>;
722 reg = <0x105c4120 0x20>;
723 #power-domain-cells = <0>;
729 reg = <0x105c4140 0x20>;
730 #power-domain-cells = <0>;
737 reg = <0x105c4180 0x20>;
738 #power-domain-cells = <0>;
744 reg = <0x105c41c0 0x20>;
745 #power-domain-cells = <0>;
751 reg = <0x10060000 0x200>;
756 #thermal-sensor-cells = <0>;
762 reg = <0x10068000 0x200>;
767 #thermal-sensor-cells = <0>;
773 reg = <0x10070000 0x200>;
778 #thermal-sensor-cells = <0>;
784 reg = <0x10078000 0x200>;
789 #thermal-sensor-cells = <0>;
795 reg = <0x1007c000 0x200>;
800 #thermal-sensor-cells = <0>;
807 reg = <0x101c0000 0x800>;
826 reg = <0x10480000 0x2000>;
832 reg = <0x10490000 0x2000>;
838 reg = <0x104b0000 0x2000>;
844 reg = <0x104c0000 0x2000>;
850 reg = <0x10580000 0x1a20>, <0x11090000 0x100>;
860 reg = <0x114b0000 0x1000>;
867 reg = <0x10fe0000 0x1000>;
873 reg = <0x14ca0000 0x1000>;
879 reg = <0x14cb0000 0x1000>;
885 reg = <0x15690000 0x1000>;
891 reg = <0x11090000 0x1000>;
897 reg = <0x14cd0000 0x1000>;
903 reg = <0x14cc0000 0x1100>;
909 reg = <0x14ce0000 0x1100>;
915 reg = <0x105c0000 0x5008>;
931 offset = <0x400>; /* SWRESET */
932 mask = <0x1>;
940 reg = <0x11001000 0x1000>,
941 <0x11002000 0x2000>,
942 <0x11004000 0x2000>,
943 <0x11006000 0x2000>;
944 interrupts = <GIC_PPI 9 0xf04>;
949 reg = <0x13800000 0x2104>;
978 #size-cells = <0>;
980 port@0 {
981 reg = <0>;
992 reg = <0x13880000 0x20b8>;
1022 reg = <0x13900000 0xc0>;
1039 #size-cells = <0>;
1043 #size-cells = <0>;
1045 port@0 {
1046 reg = <0>;
1056 reg = <0x13930000 0x48>;
1066 #size-cells = <0>;
1068 port@0 {
1069 reg = <0>;
1087 reg = <0x13970000 0x70000>;
1107 #sound-dai-cells = <0>;
1112 reg = <0x13af0000 0x80>;
1118 reg = <0x13b80000 0x1010>;
1124 reg = <0x120f0000 0x1020>;
1130 reg = <0x145f0000 0x1038>;
1136 reg = <0x156f0000 0x1044>;
1141 reg = <0x13c00000 0x1000>;
1156 reg = <0x13c10000 0x1000>;
1171 reg = <0x13c20000 0x1000>;
1186 reg = <0x14ac0000 0x5000>;
1237 reg = <0x15000000 0x1294>;
1238 interrupts = <0 402 IRQ_TYPE_LEVEL_HIGH>;
1249 reg = <0x15010000 0x1294>;
1250 interrupts = <0 403 IRQ_TYPE_LEVEL_HIGH>;
1261 reg = <0x15020000 0x10000>;
1274 reg = <0x152e0000 0x10000>;
1287 reg = <0x13a00000 0x1000>;
1293 #iommu-cells = <0>;
1298 reg = <0x13a10000 0x1000>;
1303 #iommu-cells = <0>;
1309 reg = <0x13a20000 0x1000>;
1314 #iommu-cells = <0>;
1320 reg = <0x13a30000 0x1000>;
1325 #iommu-cells = <0>;
1331 reg = <0x13c80000 0x1000>;
1336 #iommu-cells = <0>;
1342 reg = <0x13c90000 0x1000>;
1347 #iommu-cells = <0>;
1353 reg = <0x13ca0000 0x1000>;
1358 #iommu-cells = <0>;
1364 reg = <0x15040000 0x1000>;
1369 #iommu-cells = <0>;
1375 reg = <0x15050000 0x1000>;
1380 #iommu-cells = <0>;
1386 reg = <0x15060000 0x1000>;
1391 #iommu-cells = <0>;
1397 reg = <0x15200000 0x1000>;
1402 #iommu-cells = <0>;
1408 reg = <0x15210000 0x1000>;
1413 #iommu-cells = <0>;
1419 reg = <0x14c10000 0x100>;
1425 pinctrl-0 = <&uart0_bus>;
1431 reg = <0x14c20000 0x100>;
1437 pinctrl-0 = <&uart1_bus>;
1443 reg = <0x14c30000 0x100>;
1449 pinctrl-0 = <&uart2_bus>;
1455 reg = <0x14d20000 0x100>;
1460 #size-cells = <0>;
1465 samsung,spi-src-clk = <0>;
1467 pinctrl-0 = <&spi0_bus>;
1474 reg = <0x14d30000 0x100>;
1479 #size-cells = <0>;
1484 samsung,spi-src-clk = <0>;
1486 pinctrl-0 = <&spi1_bus>;
1493 reg = <0x14d40000 0x100>;
1498 #size-cells = <0>;
1503 samsung,spi-src-clk = <0>;
1505 pinctrl-0 = <&spi2_bus>;
1512 reg = <0x14d50000 0x100>;
1517 #size-cells = <0>;
1522 samsung,spi-src-clk = <0>;
1524 pinctrl-0 = <&spi3_bus>;
1531 reg = <0x14d00000 0x100>;
1536 #size-cells = <0>;
1541 samsung,spi-src-clk = <0>;
1543 pinctrl-0 = <&spi4_bus>;
1550 reg = <0x14d10000 0x100>;
1560 reg = <0x14d60000 0x100>;
1575 reg = <0x14dd0000 0x100>;
1581 samsung,pwm-outputs = <0>, <1>, <2>, <3>;
1590 reg = <0x14e40000 0x1000>;
1593 #size-cells = <0>;
1595 pinctrl-0 = <&hs_i2c0_bus>;
1603 reg = <0x14e50000 0x1000>;
1606 #size-cells = <0>;
1608 pinctrl-0 = <&hs_i2c1_bus>;
1616 reg = <0x14e60000 0x1000>;
1619 #size-cells = <0>;
1621 pinctrl-0 = <&hs_i2c2_bus>;
1629 reg = <0x14e70000 0x1000>;
1632 #size-cells = <0>;
1634 pinctrl-0 = <&hs_i2c3_bus>;
1642 reg = <0x14ec0000 0x1000>;
1645 #size-cells = <0>;
1647 pinctrl-0 = <&hs_i2c4_bus>;
1655 reg = <0x14ed0000 0x1000>;
1658 #size-cells = <0>;
1660 pinctrl-0 = <&hs_i2c5_bus>;
1668 reg = <0x14ee0000 0x1000>;
1671 #size-cells = <0>;
1673 pinctrl-0 = <&hs_i2c6_bus>;
1681 reg = <0x14ef0000 0x1000>;
1684 #size-cells = <0>;
1686 pinctrl-0 = <&hs_i2c7_bus>;
1694 reg = <0x14d90000 0x1000>;
1697 #size-cells = <0>;
1699 pinctrl-0 = <&hs_i2c8_bus>;
1707 reg = <0x14da0000 0x1000>;
1710 #size-cells = <0>;
1712 pinctrl-0 = <&hs_i2c9_bus>;
1720 reg = <0x14de0000 0x1000>;
1723 #size-cells = <0>;
1725 pinctrl-0 = <&hs_i2c10_bus>;
1733 reg = <0x14df0000 0x1000>;
1736 #size-cells = <0>;
1738 pinctrl-0 = <&hs_i2c11_bus>;
1753 ranges = <0x0 0x15400000 0x10000>;
1756 usbdrd_dwc3: usb@0 {
1762 reg = <0x0 0x10000>;
1764 phys = <&usbdrd30_phy 0>, <&usbdrd30_phy 1>;
1771 reg = <0x15500000 0x100>;
1785 reg = <0x15580000 0x100>;
1806 ranges = <0x0 0x15a00000 0x10000>;
1809 usbhost_dwc3: usb@0 {
1815 reg = <0x0 0x10000>;
1817 phys = <&usbhost30_phy 0>, <&usbhost30_phy 1>;
1826 #size-cells = <0>;
1827 reg = <0x15540000 0x2000>;
1831 fifo-depth = <0x40>;
1839 #size-cells = <0>;
1840 reg = <0x15550000 0x2000>;
1844 fifo-depth = <0x40>;
1852 #size-cells = <0>;
1853 reg = <0x15560000 0x2000>;
1857 fifo-depth = <0x40>;
1863 reg = <0x15610000 0x1000>;
1872 reg = <0x15600000 0x1000>;
1881 reg = <0x11400000 0x100>, <0x11500000 0x08>;
1891 reg = <0x11420000 0x1000>;
1901 reg = <0x11440000 0x100>;
1902 dmas = <&adma 0>, <&adma 2>;
1906 #size-cells = <0>;
1913 pinctrl-0 = <&i2s0_bus>;
1921 reg = <0x11460000 0x100>;
1927 pinctrl-0 = <&uart_aud_bus>;
1935 reg = <0x15680000 0x1000>;
1938 #phy-cells = <0>;
1944 reg = <0x15700000 0x1000>, <0x156b0000 0x1000>,
1945 <0x0c000000 0x1000>;
1957 bus-range = <0x00 0xff>;
1959 ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>,
1960 <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>;