Lines Matching +full:cpu +full:- +full:crit
4 * Copyright(c) 2015-2017 Broadcom. All rights reserved.
33 #include <dt-bindings/interrupt-controller/arm-gic.h>
37 interrupt-parent = <&gic>;
38 #address-cells = <2>;
39 #size-cells = <2>;
42 #address-cells = <2>;
43 #size-cells = <0>;
45 cpu@0 {
46 device_type = "cpu";
47 compatible = "arm,cortex-a72";
49 enable-method = "psci";
50 next-level-cache = <&CLUSTER0_L2>;
53 cpu@1 {
54 device_type = "cpu";
55 compatible = "arm,cortex-a72";
57 enable-method = "psci";
58 next-level-cache = <&CLUSTER0_L2>;
61 cpu@100 {
62 device_type = "cpu";
63 compatible = "arm,cortex-a72";
65 enable-method = "psci";
66 next-level-cache = <&CLUSTER1_L2>;
69 cpu@101 {
70 device_type = "cpu";
71 compatible = "arm,cortex-a72";
73 enable-method = "psci";
74 next-level-cache = <&CLUSTER1_L2>;
77 cpu@200 {
78 device_type = "cpu";
79 compatible = "arm,cortex-a72";
81 enable-method = "psci";
82 next-level-cache = <&CLUSTER2_L2>;
85 cpu@201 {
86 device_type = "cpu";
87 compatible = "arm,cortex-a72";
89 enable-method = "psci";
90 next-level-cache = <&CLUSTER2_L2>;
93 cpu@300 {
94 device_type = "cpu";
95 compatible = "arm,cortex-a72";
97 enable-method = "psci";
98 next-level-cache = <&CLUSTER3_L2>;
101 cpu@301 {
102 device_type = "cpu";
103 compatible = "arm,cortex-a72";
105 enable-method = "psci";
106 next-level-cache = <&CLUSTER3_L2>;
109 CLUSTER0_L2: l2-cache@0 {
111 cache-level = <2>;
112 cache-unified;
115 CLUSTER1_L2: l2-cache@100 {
117 cache-level = <2>;
118 cache-unified;
121 CLUSTER2_L2: l2-cache@200 {
123 cache-level = <2>;
124 cache-unified;
127 CLUSTER3_L2: l2-cache@300 {
129 cache-level = <2>;
130 cache-unified;
140 compatible = "arm,psci-0.2";
145 compatible = "arm,armv8-pmuv3";
150 compatible = "arm,armv8-timer";
158 compatible = "brcm,sr-mhb", "syscon";
163 compatible = "simple-bus";
164 #address-cells = <1>;
165 #size-cells = <1>;
169 compatible = "arm,ccn-502";
174 gic: interrupt-controller@2c00000 {
175 compatible = "arm,gic-v3";
176 #interrupt-cells = <3>;
177 #address-cells = <1>;
178 #size-cells = <1>;
180 interrupt-controller;
185 gic_its: msi-controller@63c20000 {
186 compatible = "arm,gic-v3-its";
187 msi-controller;
188 #msi-cells = <1>;
194 compatible = "arm,mmu-500";
196 #global-interrupts = <1>;
262 #iommu-cells = <2>;
267 compatible = "simple-bus";
268 #address-cells = <1>;
269 #size-cells = <1>;
272 #include "stingray-clock.dtsi"
275 compatible = "brcm,ocotp-v2";
277 brcm,ocotp-size = <2048>;
282 compatible = "brcm,sr-cdru", "syscon";
287 compatible = "brcm,iproc-gpio";
290 #gpio-cells = <2>;
291 gpio-controller;
295 #include "stingray-fs4.dtsi"
296 #include "stingray-pcie.dtsi"
297 #include "stingray-usb.dtsi"
300 compatible = "simple-bus";
301 #address-cells = <1>;
302 #size-cells = <1>;
305 #include "stingray-pinctrl.dtsi"
307 mdio_mux_iproc: mdio-mux@20000 {
308 compatible = "brcm,mdio-mux-iproc";
310 #address-cells = <1>;
311 #size-cells = <0>;
315 #address-cells = <1>;
316 #size-cells = <0>;
321 #address-cells = <1>;
322 #size-cells = <0>;
327 #address-cells = <1>;
328 #size-cells = <0>;
333 compatible = "brcm,iproc-pwm";
336 #pwm-cells = <3>;
347 clock-names = "timer1", "timer2", "apb_pclk";
358 clock-names = "timer1", "timer2", "apb_pclk";
368 clock-names = "timer1", "timer2", "apb_pclk";
379 clock-names = "timer1", "timer2", "apb_pclk";
390 clock-names = "timer1", "timer2", "apb_pclk";
401 clock-names = "timer1", "timer2", "apb_pclk";
412 clock-names = "timer1", "timer2", "apb_pclk";
423 clock-names = "timer1", "timer2", "apb_pclk";
428 compatible = "brcm,iproc-i2c";
430 #address-cells = <1>;
431 #size-cells = <0>;
433 clock-frequency = <100000>;
442 clock-names = "wdog_clk", "apb_pclk";
443 timeout-sec = <60>;
447 compatible = "brcm,iproc-gpio";
450 #gpio-cells = <2>;
451 gpio-controller;
452 interrupt-controller;
454 gpio-ranges = <&pinmux 0 0 16>,
472 compatible = "brcm,iproc-i2c";
474 #address-cells = <1>;
475 #size-cells = <0>;
477 clock-frequency = <100000>;
482 compatible = "snps,dw-apb-uart";
484 reg-shift = <2>;
485 clock-frequency = <25000000>;
486 interrupt-parent = <&gic>;
492 compatible = "snps,dw-apb-uart";
494 reg-shift = <2>;
495 clock-frequency = <25000000>;
496 interrupt-parent = <&gic>;
502 compatible = "snps,dw-apb-uart";
504 reg-shift = <2>;
505 clock-frequency = <25000000>;
506 interrupt-parent = <&gic>;
512 compatible = "snps,dw-apb-uart";
514 reg-shift = <2>;
515 clock-frequency = <25000000>;
516 interrupt-parent = <&gic>;
526 clock-names = "sspclk", "apb_pclk";
527 num-cs = <1>;
528 #address-cells = <1>;
529 #size-cells = <0>;
538 clock-names = "sspclk", "apb_pclk";
539 num-cs = <1>;
540 #address-cells = <1>;
541 #size-cells = <0>;
546 compatible = "brcm,iproc-rng200";
550 dma0: dma-controller@310000 {
562 #dma-cells = <1>;
564 clock-names = "apb_pclk";
571 reg-names = "amac_base";
572 dma-coherent;
578 compatible = "brcm,nand-iproc", "brcm,brcmnand-v6.1";
582 reg-names = "nand", "iproc-idm", "iproc-ext";
584 #address-cells = <1>;
585 #size-cells = <0>;
586 brcm,nand-has-wp;
591 compatible = "brcm,sdhci-iproc";
594 bus-width = <8>;
601 compatible = "brcm,sdhci-iproc";
604 bus-width = <8>;
612 compatible = "simple-bus";
613 #address-cells = <1>;
614 #size-cells = <1>;
618 compatible = "brcm,sr-thermal";
620 brcm,tmon-mask = <0x3f>;
621 #thermal-sensor-cells = <1>;
625 thermal-zones {
626 ihost0_thermal: ihost0-thermal {
627 polling-delay-passive = <0>;
628 polling-delay = <1000>;
629 thermal-sensors = <&tmon 0>;
631 cpu-crit {
638 ihost1_thermal: ihost1-thermal {
639 polling-delay-passive = <0>;
640 polling-delay = <1000>;
641 thermal-sensors = <&tmon 1>;
643 cpu-crit {
650 ihost2_thermal: ihost2-thermal {
651 polling-delay-passive = <0>;
652 polling-delay = <1000>;
653 thermal-sensors = <&tmon 2>;
655 cpu-crit {
662 ihost3_thermal: ihost3-thermal {
663 polling-delay-passive = <0>;
664 polling-delay = <1000>;
665 thermal-sensors = <&tmon 3>;
667 cpu-crit {
674 crmu_thermal: crmu-thermal {
675 polling-delay-passive = <0>;
676 polling-delay = <1000>;
677 thermal-sensors = <&tmon 4>;
679 cpu-crit {
686 nitro_thermal: nitro-thermal {
687 polling-delay-passive = <0>;
688 polling-delay = <1000>;
689 thermal-sensors = <&tmon 5>;
691 cpu-crit {
700 nic-hsls {
701 compatible = "simple-bus";
702 #address-cells = <1>;
703 #size-cells = <1>;
707 compatible = "brcm,iproc-nic-i2c";
708 #address-cells = <1>;
709 #size-cells = <0>;
712 brcm,ape-hsls-addr-mask = <0x03400000>;
713 clock-frequency = <100000>;