Lines Matching +full:iommu +full:- +full:map +full:- +full:mask
1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
10 nco: clock-controller@28e03c000 {
11 compatible = "apple,t6000-nco", "apple,nco";
14 #clock-cells = <1>;
17 aic: interrupt-controller@28e100000 {
18 compatible = "apple,t6000-aic", "apple,aic2";
19 #interrupt-cells = <4>;
20 interrupt-controller;
23 reg-names = "core", "event";
24 power-domains = <&ps_aic>;
28 compatible = "apple,t6000-pinctrl", "apple,pinctrl";
31 gpio-controller;
32 #gpio-cells = <2>;
33 gpio-ranges = <&pinctrl_smc 0 0 30>;
36 interrupt-controller;
37 #interrupt-cells = <2>;
38 interrupt-parent = <&aic>;
49 compatible = "apple,t6000-wdt", "apple,wdt";
52 interrupt-parent = <&aic>;
56 sio_dart_0: iommu@39b004000 {
57 compatible = "apple,t6000-dart";
59 interrupt-parent = <&aic>;
61 #iommu-cells = <1>;
62 power-domains = <&ps_sio_cpu>;
65 sio_dart_1: iommu@39b008000 {
66 compatible = "apple,t6000-dart";
68 interrupt-parent = <&aic>;
70 #iommu-cells = <1>;
71 power-domains = <&ps_sio_cpu>;
75 compatible = "apple,t6000-fpwm", "apple,s5l-fpwm";
77 power-domains = <&ps_fpwm0>;
79 #pwm-cells = <2>;
84 compatible = "apple,t6000-i2c", "apple,i2c";
87 interrupt-parent = <&aic>;
89 pinctrl-0 = <&i2c0_pins>;
90 pinctrl-names = "default";
91 power-domains = <&ps_i2c0>;
92 #address-cells = <0x1>;
93 #size-cells = <0x0>;
97 compatible = "apple,t6000-i2c", "apple,i2c";
100 interrupt-parent = <&aic>;
102 pinctrl-0 = <&i2c1_pins>;
103 pinctrl-names = "default";
104 power-domains = <&ps_i2c1>;
105 #address-cells = <0x1>;
106 #size-cells = <0x0>;
111 compatible = "apple,t6000-i2c", "apple,i2c";
114 interrupt-parent = <&aic>;
116 pinctrl-0 = <&i2c2_pins>;
117 pinctrl-names = "default";
118 power-domains = <&ps_i2c2>;
119 #address-cells = <0x1>;
120 #size-cells = <0x0>;
125 compatible = "apple,t6000-i2c", "apple,i2c";
128 interrupt-parent = <&aic>;
130 pinctrl-0 = <&i2c3_pins>;
131 pinctrl-names = "default";
132 power-domains = <&ps_i2c3>;
133 #address-cells = <0x1>;
134 #size-cells = <0x0>;
139 compatible = "apple,t6000-i2c", "apple,i2c";
142 interrupt-parent = <&aic>;
144 pinctrl-0 = <&i2c4_pins>;
145 pinctrl-names = "default";
146 power-domains = <&ps_i2c4>;
147 #address-cells = <0x1>;
148 #size-cells = <0x0>;
153 compatible = "apple,t6000-i2c", "apple,i2c";
156 interrupt-parent = <&aic>;
158 pinctrl-0 = <&i2c5_pins>;
159 pinctrl-names = "default";
160 power-domains = <&ps_i2c5>;
161 #address-cells = <0x1>;
162 #size-cells = <0x0>;
167 compatible = "apple,s5l-uart";
169 reg-io-width = <4>;
170 interrupt-parent = <&aic>;
177 clock-names = "uart", "clk_uart_baud0";
178 power-domains = <&ps_uart0>;
182 admac: dma-controller@39b400000 {
183 compatible = "apple,t6000-admac", "apple,admac";
185 #dma-cells = <1>;
186 dma-channels = <16>;
187 interrupts-extended = <0>,
192 power-domains = <&ps_sio_adma>;
197 compatible = "apple,t6000-mca", "apple,mca";
205 dma-names = "tx0a", "rx0a", "tx0b", "rx0b",
209 interrupt-parent = <&aic>;
214 power-domains = <&ps_audio_p>, <&ps_mca0>, <&ps_mca1>,
217 #sound-dai-cells = <1>;
220 pcie0_dart_0: iommu@581008000 {
221 compatible = "apple,t6000-dart";
223 #iommu-cells = <1>;
224 interrupt-parent = <&aic>;
226 power-domains = <&ps_apcie_gp_sys>;
229 pcie0_dart_1: iommu@582008000 {
230 compatible = "apple,t6000-dart";
232 #iommu-cells = <1>;
233 interrupt-parent = <&aic>;
235 power-domains = <&ps_apcie_gp_sys>;
238 pcie0_dart_2: iommu@583008000 {
239 compatible = "apple,t6000-dart";
241 #iommu-cells = <1>;
242 interrupt-parent = <&aic>;
244 power-domains = <&ps_apcie_gp_sys>;
248 pcie0_dart_3: iommu@584008000 {
249 compatible = "apple,t6000-dart";
251 #iommu-cells = <1>;
252 interrupt-parent = <&aic>;
254 power-domains = <&ps_apcie_gp_sys>;
259 compatible = "apple,t6000-pcie", "apple,pcie";
268 reg-names = "config", "rc", "port0", "port1", "port2", "port3";
270 interrupt-parent = <&aic>;
276 msi-controller;
277 msi-parent = <&pcie0>;
278 msi-ranges = <&aic AIC_IRQ 0 1581 IRQ_TYPE_EDGE_RISING 32>;
281 iommu-map = <0x100 &pcie0_dart_0 1 1>,
285 iommu-map-mask = <0xff00>;
287 bus-range = <0 4>;
288 #address-cells = <3>;
289 #size-cells = <2>;
293 power-domains = <&ps_apcie_gp_sys>;
294 pinctrl-0 = <&pcie_pins>;
295 pinctrl-names = "default";
300 reset-gpios = <&pinctrl_ap 4 GPIO_ACTIVE_LOW>;
302 #address-cells = <3>;
303 #size-cells = <2>;
306 interrupt-controller;
307 #interrupt-cells = <1>;
309 interrupt-map-mask = <0 0 0 7>;
310 interrupt-map = <0 0 0 1 &port00 0 0 0 0>,
319 reset-gpios = <&pinctrl_ap 5 GPIO_ACTIVE_LOW>;
321 #address-cells = <3>;
322 #size-cells = <2>;
325 interrupt-controller;
326 #interrupt-cells = <1>;
328 interrupt-map-mask = <0 0 0 7>;
329 interrupt-map = <0 0 0 1 &port01 0 0 0 0>,
338 reset-gpios = <&pinctrl_ap 6 GPIO_ACTIVE_LOW>;
340 #address-cells = <3>;
341 #size-cells = <2>;
344 interrupt-controller;
345 #interrupt-cells = <1>;
347 interrupt-map-mask = <0 0 0 7>;
348 interrupt-map = <0 0 0 1 &port02 0 0 0 0>,
358 reset-gpios = <&pinctrl_ap 7 GPIO_ACTIVE_LOW>;
360 #address-cells = <3>;
361 #size-cells = <2>;
364 interrupt-controller;
365 #interrupt-cells = <1>;
367 interrupt-map-mask = <0 0 0 7>;
368 interrupt-map = <0 0 0 1 &port03 0 0 0 0>,