Lines Matching +full:phy +full:- +full:sata3
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * dts file for AppliedMicro (APM) X-Gene Storm SOC
9 compatible = "apm,xgene-storm";
10 interrupt-parent = <&gic>;
11 #address-cells = <2>;
12 #size-cells = <2>;
15 #address-cells = <2>;
16 #size-cells = <0>;
22 enable-method = "spin-table";
23 cpu-release-addr = <0x1 0x0000fff8>;
24 next-level-cache = <&xgene_L2_0>;
30 enable-method = "spin-table";
31 cpu-release-addr = <0x1 0x0000fff8>;
32 next-level-cache = <&xgene_L2_0>;
38 enable-method = "spin-table";
39 cpu-release-addr = <0x1 0x0000fff8>;
40 next-level-cache = <&xgene_L2_1>;
46 enable-method = "spin-table";
47 cpu-release-addr = <0x1 0x0000fff8>;
48 next-level-cache = <&xgene_L2_1>;
54 enable-method = "spin-table";
55 cpu-release-addr = <0x1 0x0000fff8>;
56 next-level-cache = <&xgene_L2_2>;
62 enable-method = "spin-table";
63 cpu-release-addr = <0x1 0x0000fff8>;
64 next-level-cache = <&xgene_L2_2>;
70 enable-method = "spin-table";
71 cpu-release-addr = <0x1 0x0000fff8>;
72 next-level-cache = <&xgene_L2_3>;
78 enable-method = "spin-table";
79 cpu-release-addr = <0x1 0x0000fff8>;
80 next-level-cache = <&xgene_L2_3>;
82 xgene_L2_0: l2-cache-0 {
84 cache-level = <2>;
85 cache-unified;
87 xgene_L2_1: l2-cache-1 {
89 cache-level = <2>;
90 cache-unified;
92 xgene_L2_2: l2-cache-2 {
94 cache-level = <2>;
95 cache-unified;
97 xgene_L2_3: l2-cache-3 {
99 cache-level = <2>;
100 cache-unified;
104 gic: interrupt-controller@78010000 {
105 compatible = "arm,cortex-a15-gic";
106 #interrupt-cells = <3>;
107 interrupt-controller;
116 compatible = "arm,armv8-timer";
118 <1 13 0xff08>, /* Non-secure Phys IRQ */
121 clock-frequency = <50000000>;
125 compatible = "apm,potenza-pmu", "arm,armv8-pmuv3";
130 compatible = "simple-bus";
131 #address-cells = <2>;
132 #size-cells = <2>;
134 dma-ranges = <0x0 0x0 0x0 0x0 0x400 0x0>;
137 #address-cells = <2>;
138 #size-cells = <2>;
141 compatible = "fixed-clock";
142 #clock-cells = <1>;
143 clock-frequency = <100000000>;
144 clock-output-names = "refclk";
148 compatible = "apm,xgene-pcppll-clock";
149 #clock-cells = <1>;
151 clock-names = "pcppll";
153 clock-output-names = "pcppll";
158 compatible = "apm,xgene-socpll-clock";
159 #clock-cells = <1>;
161 clock-names = "socpll";
163 clock-output-names = "socpll";
168 compatible = "fixed-factor-clock";
169 #clock-cells = <1>;
171 clock-names = "socplldiv2";
172 clock-mult = <1>;
173 clock-div = <2>;
174 clock-output-names = "socplldiv2";
178 compatible = "apm,xgene-device-clock";
179 #clock-cells = <1>;
182 reg-names = "div-reg";
183 divider-offset = <0x164>;
184 divider-width = <0x5>;
185 divider-shift = <0x0>;
186 clock-output-names = "ahbclk";
190 compatible = "apm,xgene-device-clock";
191 #clock-cells = <1>;
195 reg-names = "csr-reg", "div-reg";
196 csr-offset = <0x0>;
197 csr-mask = <0x2>;
198 enable-offset = <0x8>;
199 enable-mask = <0x2>;
200 divider-offset = <0x178>;
201 divider-width = <0x8>;
202 divider-shift = <0x0>;
203 clock-output-names = "sdioclk";
207 compatible = "apm,xgene-device-clock";
208 #clock-cells = <1>;
210 clock-names = "ethclk";
212 reg-names = "div-reg";
213 divider-offset = <0x238>;
214 divider-width = <0x9>;
215 divider-shift = <0x0>;
216 clock-output-names = "ethclk";
220 compatible = "apm,xgene-device-clock";
221 #clock-cells = <1>;
224 reg-names = "csr-reg";
225 clock-output-names = "menetclk";
229 compatible = "apm,xgene-device-clock";
230 #clock-cells = <1>;
233 reg-names = "csr-reg";
234 csr-mask = <0xa>;
235 enable-mask = <0xf>;
236 clock-output-names = "sge0clk";
240 compatible = "apm,xgene-device-clock";
241 #clock-cells = <1>;
244 reg-names = "csr-reg";
245 csr-mask = <0x3>;
246 clock-output-names = "xge0clk";
250 compatible = "apm,xgene-device-clock";
252 #clock-cells = <1>;
255 reg-names = "csr-reg";
256 csr-mask = <0x3>;
257 clock-output-names = "xge1clk";
261 compatible = "apm,xgene-device-clock";
262 #clock-cells = <1>;
265 reg-names = "csr-reg";
266 clock-output-names = "sataphy1clk";
268 csr-offset = <0x4>;
269 csr-mask = <0x00>;
270 enable-offset = <0x0>;
271 enable-mask = <0x06>;
275 compatible = "apm,xgene-device-clock";
276 #clock-cells = <1>;
279 reg-names = "csr-reg";
280 clock-output-names = "sataphy2clk";
282 csr-offset = <0x4>;
283 csr-mask = <0x3a>;
284 enable-offset = <0x0>;
285 enable-mask = <0x06>;
289 compatible = "apm,xgene-device-clock";
290 #clock-cells = <1>;
293 reg-names = "csr-reg";
294 clock-output-names = "sataphy3clk";
296 csr-offset = <0x4>;
297 csr-mask = <0x3a>;
298 enable-offset = <0x0>;
299 enable-mask = <0x06>;
303 compatible = "apm,xgene-device-clock";
304 #clock-cells = <1>;
307 reg-names = "csr-reg";
308 clock-output-names = "sata01clk";
309 csr-offset = <0x4>;
310 csr-mask = <0x05>;
311 enable-offset = <0x0>;
312 enable-mask = <0x39>;
316 compatible = "apm,xgene-device-clock";
317 #clock-cells = <1>;
320 reg-names = "csr-reg";
321 clock-output-names = "sata23clk";
322 csr-offset = <0x4>;
323 csr-mask = <0x05>;
324 enable-offset = <0x0>;
325 enable-mask = <0x39>;
329 compatible = "apm,xgene-device-clock";
330 #clock-cells = <1>;
333 reg-names = "csr-reg";
334 clock-output-names = "sata45clk";
335 csr-offset = <0x4>;
336 csr-mask = <0x05>;
337 enable-offset = <0x0>;
338 enable-mask = <0x39>;
342 compatible = "apm,xgene-device-clock";
343 #clock-cells = <1>;
346 reg-names = "csr-reg";
347 csr-offset = <0xc>;
348 csr-mask = <0x2>;
349 enable-offset = <0x10>;
350 enable-mask = <0x2>;
351 clock-output-names = "rtcclk";
355 compatible = "apm,xgene-device-clock";
356 #clock-cells = <1>;
359 reg-names = "csr-reg";
360 csr-offset = <0xc>;
361 csr-mask = <0x10>;
362 enable-offset = <0x10>;
363 enable-mask = <0x10>;
364 clock-output-names = "rngpkaclk";
369 compatible = "apm,xgene-device-clock";
370 #clock-cells = <1>;
373 reg-names = "csr-reg";
374 clock-output-names = "pcie0clk";
379 compatible = "apm,xgene-device-clock";
380 #clock-cells = <1>;
383 reg-names = "csr-reg";
384 clock-output-names = "pcie1clk";
389 compatible = "apm,xgene-device-clock";
390 #clock-cells = <1>;
393 reg-names = "csr-reg";
394 clock-output-names = "pcie2clk";
399 compatible = "apm,xgene-device-clock";
400 #clock-cells = <1>;
403 reg-names = "csr-reg";
404 clock-output-names = "pcie3clk";
409 compatible = "apm,xgene-device-clock";
410 #clock-cells = <1>;
413 reg-names = "csr-reg";
414 clock-output-names = "pcie4clk";
418 compatible = "apm,xgene-device-clock";
419 #clock-cells = <1>;
422 reg-names = "csr-reg";
423 clock-output-names = "dmaclk";
428 compatible = "apm,xgene1-msi";
429 msi-controller;
449 scu: system-clk-controller@17000000 {
450 compatible = "apm,xgene-scu","syscon";
455 compatible = "syscon-reboot";
462 compatible = "apm,xgene-csw", "syscon";
467 compatible = "apm,xgene-mcb", "syscon";
472 compatible = "apm,xgene-mcb", "syscon";
477 compatible = "apm,xgene-efuse", "syscon";
482 compatible = "apm,xgene-rb", "syscon";
487 compatible = "apm,xgene-edac";
488 #address-cells = <2>;
489 #size-cells = <2>;
491 regmap-csw = <&csw>;
492 regmap-mcba = <&mcba>;
493 regmap-mcbb = <&mcbb>;
494 regmap-efuse = <&efuse>;
495 regmap-rb = <&rb>;
502 compatible = "apm,xgene-edac-mc";
504 memory-controller = <0>;
508 compatible = "apm,xgene-edac-mc";
510 memory-controller = <1>;
514 compatible = "apm,xgene-edac-mc";
516 memory-controller = <2>;
520 compatible = "apm,xgene-edac-mc";
522 memory-controller = <3>;
526 compatible = "apm,xgene-edac-pmd";
528 pmd-controller = <0>;
532 compatible = "apm,xgene-edac-pmd";
534 pmd-controller = <1>;
538 compatible = "apm,xgene-edac-pmd";
540 pmd-controller = <2>;
544 compatible = "apm,xgene-edac-pmd";
546 pmd-controller = <3>;
550 compatible = "apm,xgene-edac-l3";
555 compatible = "apm,xgene-edac-soc-v1";
561 compatible = "apm,xgene-pmu-v2";
562 #address-cells = <2>;
563 #size-cells = <2>;
565 regmap-csw = <&csw>;
566 regmap-mcba = <&mcba>;
567 regmap-mcbb = <&mcbb>;
572 compatible = "apm,xgene-pmu-l3c";
577 compatible = "apm,xgene-pmu-iob";
582 compatible = "apm,xgene-pmu-mcb";
584 enable-bit-index = <0>;
588 compatible = "apm,xgene-pmu-mcb";
590 enable-bit-index = <1>;
594 compatible = "apm,xgene-pmu-mc";
596 enable-bit-index = <0>;
600 compatible = "apm,xgene-pmu-mc";
602 enable-bit-index = <1>;
606 compatible = "apm,xgene-pmu-mc";
608 enable-bit-index = <2>;
612 compatible = "apm,xgene-pmu-mc";
614 enable-bit-index = <3>;
621 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
622 #interrupt-cells = <1>;
623 #size-cells = <2>;
624 #address-cells = <3>;
627 reg-names = "csr", "cfg";
631 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
633 bus-range = <0x00 0xff>;
634 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
635 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x4
639 dma-coherent;
641 msi-parent = <&msi>;
647 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
648 #interrupt-cells = <1>;
649 #size-cells = <2>;
650 #address-cells = <3>;
653 reg-names = "csr", "cfg";
657 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
659 bus-range = <0x00 0xff>;
660 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
661 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc8 0x4
665 dma-coherent;
667 msi-parent = <&msi>;
673 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
674 #interrupt-cells = <1>;
675 #size-cells = <2>;
676 #address-cells = <3>;
679 reg-names = "csr", "cfg";
683 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
685 bus-range = <0x00 0xff>;
686 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
687 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xce 0x4
691 dma-coherent;
693 msi-parent = <&msi>;
699 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
700 #interrupt-cells = <1>;
701 #size-cells = <2>;
702 #address-cells = <3>;
705 reg-names = "csr", "cfg";
709 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
711 bus-range = <0x00 0xff>;
712 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
713 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xd4 0x4
717 dma-coherent;
719 msi-parent = <&msi>;
725 compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie";
726 #interrupt-cells = <1>;
727 #size-cells = <2>;
728 #address-cells = <3>;
731 reg-names = "csr", "cfg";
735 dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000
737 bus-range = <0x00 0xff>;
738 interrupt-map-mask = <0x0 0x0 0x0 0x7>;
739 interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xda 0x4
743 dma-coherent;
745 msi-parent = <&msi>;
749 compatible = "apm,xgene-slimpro-mbox";
751 #mbox-cells = <1>;
763 compatible = "apm,xgene-slimpro-i2c";
768 compatible = "apm,xgene-slimpro-hwmon";
776 reg-shift = <2>;
777 clock-frequency = <10000000>; /* Updated by bootloader */
778 interrupt-parent = <&gic>;
786 reg-shift = <2>;
787 clock-frequency = <10000000>; /* Updated by bootloader */
788 interrupt-parent = <&gic>;
796 reg-shift = <2>;
797 clock-frequency = <10000000>; /* Updated by bootloader */
798 interrupt-parent = <&gic>;
806 reg-shift = <2>;
807 clock-frequency = <10000000>; /* Updated by bootloader */
808 interrupt-parent = <&gic>;
813 compatible = "arasan,sdhci-4.9a";
816 dma-coherent;
817 no-1-8-v;
818 clock-names = "clk_xin", "clk_ahb";
823 compatible = "apm,xgene-gpio";
825 gpio-controller;
826 #gpio-cells = <2>;
830 compatible = "snps,dw-apb-gpio";
832 #address-cells = <1>;
833 #size-cells = <0>;
835 porta: gpio-controller@0 {
836 compatible = "snps,dw-apb-gpio-port";
837 gpio-controller;
838 #gpio-cells = <2>;
839 snps,nr-gpios = <32>;
846 #address-cells = <1>;
847 #size-cells = <0>;
848 compatible = "snps,designware-i2c";
851 #clock-cells = <1>;
856 phy1: phy@1f21a000 {
857 compatible = "apm,xgene-phy";
859 #phy-cells = <1>;
862 apm,tx-boost-gain = <30 30 30 30 30 30>;
863 apm,tx-eye-tuning = <2 10 10 2 10 10>;
866 phy2: phy@1f22a000 {
867 compatible = "apm,xgene-phy";
869 #phy-cells = <1>;
872 apm,tx-boost-gain = <30 30 30 30 30 30>;
873 apm,tx-eye-tuning = <1 10 10 2 10 10>;
876 phy3: phy@1f23a000 {
877 compatible = "apm,xgene-phy";
879 #phy-cells = <1>;
882 apm,tx-boost-gain = <31 31 31 31 31 31>;
883 apm,tx-eye-tuning = <2 10 10 2 10 10>;
887 compatible = "apm,xgene-ahci";
894 dma-coherent;
898 phy-names = "sata-phy";
902 compatible = "apm,xgene-ahci";
909 dma-coherent;
913 phy-names = "sata-phy";
916 sata3: sata@1a800000 { label
917 compatible = "apm,xgene-ahci";
923 dma-coherent;
927 phy-names = "sata-phy";
930 /* Node-name might need to be coded as dwusb for backward compatibility */
936 dma-coherent;
945 dma-coherent;
950 compatible = "apm,xgene-gpio-sb";
952 #gpio-cells = <2>;
953 gpio-controller;
960 interrupt-parent = <&gic>;
961 #interrupt-cells = <2>;
962 interrupt-controller;
966 compatible = "apm,xgene-rtc";
969 #clock-cells = <1>;
974 compatible = "apm,xgene-mdio-rgmii";
975 #address-cells = <1>;
976 #size-cells = <0>;
982 compatible = "apm,xgene-enet";
987 reg-names = "enet_csr", "ring_csr", "ring_cmd";
989 dma-coherent;
992 local-mac-address = [00 00 00 00 00 00];
993 phy-connection-type = "rgmii";
994 phy-handle = <&menetphy>,<&menet0phy>;
996 compatible = "apm,xgene-mdio";
997 #address-cells = <1>;
998 #size-cells = <0>;
1000 compatible = "ethernet-phy-id001c.c915";
1008 compatible = "apm,xgene1-sgenet";
1013 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1016 dma-coherent;
1018 local-mac-address = [00 00 00 00 00 00];
1019 phy-connection-type = "sgmii";
1020 phy-handle = <&sgenet0phy>;
1024 compatible = "apm,xgene1-sgenet";
1029 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1032 port-id = <1>;
1033 dma-coherent;
1034 local-mac-address = [00 00 00 00 00 00];
1035 phy-connection-type = "sgmii";
1036 phy-handle = <&sgenet1phy>;
1040 compatible = "apm,xgene1-xgenet";
1045 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1055 dma-coherent;
1058 local-mac-address = [00 00 00 00 00 00];
1059 phy-connection-type = "xgmii";
1063 compatible = "apm,xgene1-xgenet";
1068 reg-names = "enet_csr", "ring_csr", "ring_cmd";
1071 port-id = <1>;
1072 dma-coherent;
1075 local-mac-address = [00 00 00 00 00 00];
1076 phy-connection-type = "xgmii";
1080 compatible = "apm,xgene-rng";
1087 compatible = "apm,xgene-storm-dma";
1098 dma-coherent;