Lines Matching full:workaround
431 The workaround forces KVM to explicitly set VTCR_EL2.HA to 0,
454 The workaround promotes data cache clean instructions to
456 Please note that this does not necessarily enable the workaround,
476 The workaround promotes data cache clean instructions to
478 Please note that this does not necessarily enable the workaround,
499 The workaround promotes data cache clean instructions to
502 workaround, as it depends on the alternative framework, which will
521 The workaround promotes data cache clean instructions to
523 Please note that this does not necessarily enable the workaround,
539 The workaround is to promote device loads to use Load-Acquire
541 Please note that this does not necessarily enable the workaround,
560 The workaround is to verify that the Stage 1 translation
562 Please note that this does not necessarily enable the workaround,
574 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
597 The workaround is to write the contextidr_el1 register on exception
599 Please note that this does not necessarily enable the workaround,
623 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
627 without a break-before-make. The workaround is to disable the usage
638 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
655 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
681 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
697 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
714 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
723 workaround repeats the TLBI+DSB operation.
729 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
744 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
747 This option adds a workaround for ARM Neoverse-N1 erratum
751 modified by another CPU. The workaround depends on a firmware
754 Workaround the issue by hiding the DIC feature from EL0. This
760 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
763 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
767 non-cacheable memory attributes. The workaround depends on a firmware
770 KVM guests must also have the workaround implemented or they can
786 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
788 hardware update of the page table's dirty bit. The workaround
794 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
797 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
814 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
824 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
842 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
847 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
863 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
867 Enable workaround for ARM Cortex-A710 erratum 2054223
873 Workaround is to issue two TSB consecutively on affected cores.
878 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
882 Enable workaround for ARM Neoverse-N2 erratum 2067961
888 Workaround is to issue two TSB consecutively on affected cores.
896 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
901 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
914 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
919 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
936 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
949 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
953 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
967 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
971 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
990 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
994 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
1008 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1012 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1025 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1028 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1035 mprotect() system call. Workaround the problem by doing a break-before-make
1041 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1044 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1057 Enable workaround for errata 22375 and 24313.
1136 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1146 The workaround is to ensure these bits are clear in TCR_ELx.
1147 The workaround only affects the Fujitsu-A64FX.
1224 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"