Lines Matching +full:in +full:- +full:and +full:- +full:around
1 # SPDX-License-Identifier: GPL-2.0-only
194 if $(cc-option,-fpatchable-function-entry=2)
259 ARM 64-bit (AArch64) Linux support.
269 depends on $(cc-option,-fpatchable-function-entry=2)
302 # VA_BITS - PAGE_SHIFT - 3
378 def_bool !$(as-instr,1:\n.inst 0\n.rept . - 1b\n\nnop\n.endr\n)
386 # and this was backported to 10.2.0, 9.4.0, 8.5.0, but not earlier
419 …bool "AmpereOne: AC03_CPU_38: Certain bits in the Virtualization Translation Control Register and …
422 This option adds an alternative code sequence to work around Ampere
425 The affected design reports FEAT_HAFDBS as not implemented in
433 at stage-2.
441 …bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is acce…
445 This option adds an alternative code sequence to work around ARM
446 erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
447 AXI master interface and an L2 cache.
449 If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
450 and is unable to accept a certain write via this interface, it will
451 not progress on read data presented on the read data channel and the
455 data cache clean-and-invalidate.
463 …bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to th…
467 This option adds an alternative code sequence to work around ARM
468 erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
469 master interface and an L2 cache.
477 data cache clean-and-invalidate.
485 bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
489 This option adds an alternative code sequence to work around ARM
490 erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
493 If a Cortex-A53 processor is executing a store or prefetch for
494 write instruction at the same time as a processor in another
500 data cache clean-and-invalidate.
508 bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
512 This option adds an alternative code sequence to work around ARM
513 erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
516 If the processor is executing a load and store exclusive sequence at
517 the same time as a processor in another cluster is executing a cache
522 data cache clean-and-invalidate.
530 bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
533 This option adds an alternative code sequence to work around ARM
534 erratum 832075 on Cortex-A57 parts up to r1p2.
536 Affected Cortex-A57 parts might deadlock when exclusive load/store
537 instructions to Write-Back memory are mixed with Device loads.
539 The workaround is to promote device loads to use Load-Acquire
548 …bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a…
552 This option adds an alternative code sequence to work around ARM
553 erratum 834220 on Cortex-A57 parts up to r1p2.
555 Affected Cortex-A57 parts might report a Stage 2 translation
558 alignment fault at Stage 1 and a translation fault at Stage 2.
569 …bool "Cortex-A57/A72: 1742098: ELR recorded incorrectly on interrupt taken between cryptographic i…
573 This option removes the AES hwcap for aarch32 user-space to
574 workaround erratum 1742098 on Cortex-A57 and Cortex-A72.
585 bool "Cortex-A53: 845719: a load might read incorrect data"
589 This option adds an alternative code sequence to work around ARM
590 erratum 845719 on Cortex-A53 parts up to r0p4.
592 When running a compat (AArch32) userspace on an affected Cortex-A53
598 return to a 32-bit task.
606 bool "Cortex-A53: 843419: A load or store might access an incorrect address"
609 This option links the kernel with '--fix-cortex-a53-843419' and
612 Cortex-A53 parts up to r0p4.
617 def_bool $(ld-option,--fix-cortex-a53-843419)
620 …bool "Cortex-A55: 1024718: Update of DBM/AP bits without break before make might result in incorre…
623 This option adds a workaround for ARM Cortex-A55 Erratum 1024718.
625 Affected Cortex-A55 cores (all revisions) could cause incorrect
627 without a break-before-make. The workaround is to disable the usage
634 …bool "Cortex-A76/Neoverse-N1: MRC read following MRRC read of specific Generic Timer in AArch32 mi…
638 This option adds a workaround for ARM Cortex-A76/Neoverse-N1
639 errata 1188873 and 1418040.
641 Affected Cortex-A76/Neoverse-N1 cores (r0p0 to r3p1) could
651 …bool "Cortex-A76: 1165522: Speculative AT instruction using out-of-context translation regime coul…
655 This option adds a workaround for ARM Cortex-A76 erratum 1165522.
657 Affected Cortex-A76 cores (r0p0, r1p0, r2p0) could end-up with
664 …bool "Cortex-A57/A72: 1319537: Speculative AT instruction using out-of-context translation regime …
668 This option adds work arounds for ARM Cortex-A57 erratum 1319537
669 and A72 erratum 1319367
671 Cortex-A57 and A72 cores could end-up with corrupted TLBs by
677 …bool "Cortex-A55: 1530923: Speculative AT instruction using out-of-context translation regime coul…
681 This option adds a workaround for ARM Cortex-A55 erratum 1530923.
683 Affected Cortex-A55 cores (r0p0, r0p1, r1p0, r2p0) could end-up with
693 …bool "Cortex-A55: Completion of affected memory accesses might not be guaranteed by completion of …
697 This option adds a workaround for ARM Cortex-A55 erratum #2441007.
699 Under very rare circumstances, affected Cortex-A55 CPUs
700 may not handle a race between a break-before-make sequence on one
701 CPU, and another CPU accessing the same page. This could allow a
704 Work around this by adding the affected CPUs to the list that needs
710 …bool "Cortex-A76: Modification of the translation table for a virtual address might lead to read-a…
714 This option adds a workaround for ARM Cortex-A76 erratum 1286807.
716 On the affected Cortex-A76 cores (r0p0 to r3p0), if a virtual
720 break-before-make sequence, then under very rare circumstances
726 bool "Cortex-A76: Software Step might prevent interrupt recognition"
729 This option adds a workaround for Arm Cortex-A76 erratum 1463225.
731 On the affected Cortex-A76 cores (r0p0 to r3p1), software stepping
733 subsequent interrupts when software stepping is disabled in the
734 exception handler of the system call and either kernel debugging
735 is enabled or VHE is in use.
737 Work around the erratum by triggering a dummy step exception
739 in a VHE configuration of the kernel.
744 bool "Neoverse-N1: workaround mis-ordering of instruction fetches"
747 This option adds a workaround for ARM Neoverse-N1 erratum
750 Affected Neoverse-N1 cores could execute a stale instruction when
755 forces user-space to perform cache maintenance.
760 …bool "Cortex-A77: 1508412: workaround deadlock on sequence of NC/Device load and store exclusive o…
763 This option adds a workaround for Arm Cortex-A77 erratum 1508412.
765 Affected Cortex-A77 cores (r0p0, r1p0) could deadlock on a sequence
766 of a store-exclusive or read of PAR_EL1 and a load with device or
767 non-cacheable memory attributes. The workaround depends on a firmware
773 Work around the issue by inserting DMB SY barriers around PAR_EL1
774 register reads and warning KVM users. The DMB barrier is sufficient
783 bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
786 This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
787 Affected Cortex-A510 might not respect the ordering rules for
794 bool "Cortex-A510: 2077057: workaround software-step corrupting SPSR_EL2"
797 This option adds the workaround for ARM Cortex-A510 erratum 2077057.
798 Affected Cortex-A510 may corrupt SPSR_EL2 when the a step exception is
806 previous guest entry, and can be restored from the in-memory copy.
811 bool "Cortex-A510: 2658417: remove BF16 support due to incorrect result"
814 This option adds the workaround for ARM Cortex-A510 erratum 2658417.
815 Affected Cortex-A510 (r0p0 to r1p1) may produce the wrong result for
816 BFMMLA or VMMLA instructions in rare circumstances when a pair of
819 user-space should not be using these instructions.
824 bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
829 This option adds the workaround for ARM Cortex-A710/X2 erratum 2119858.
831 Affected Cortex-A710/X2 cores could overwrite up to 3 cache lines of trace
832 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
835 Work around the issue by always making sure we move the TRBPTR_EL1 by
836 256 bytes before enabling the buffer and filling the first 256 bytes of
842 bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode"
847 This option adds the workaround for ARM Neoverse-N2 erratum 2139208.
849 Affected Neoverse-N2 cores could overwrite up to 3 cache lines of trace
850 data at the base of the buffer (pointed to by TRBASER_EL1) in FILL mode in
853 Work around the issue by always making sure we move the TRBPTR_EL1 by
854 256 bytes before enabling the buffer and filling the first 256 bytes of
863 bool "Cortex-A710: 2054223: workaround TSB instruction failing to flush trace"
867 Enable workaround for ARM Cortex-A710 erratum 2054223
870 the PE is in trace prohibited state. This will cause losing a few bytes
878 bool "Neoverse-N2: 2067961: workaround TSB instruction failing to flush trace"
882 Enable workaround for ARM Neoverse-N2 erratum 2067961
885 the PE is in trace prohibited state. This will cause losing a few bytes
896 bool "Neoverse-N2: 2253138: workaround TRBE writing to address out-of-range"
901 This option adds the workaround for ARM Neoverse-N2 erratum 2253138.
903 Affected Neoverse-N2 cores might write to an out-of-range address, not reserved
906 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
908 Work around this in the driver by always making sure that there is a
914 bool "Cortex-A710/X2: 2224489: workaround TRBE writing to address out-of-range"
919 This option adds the workaround for ARM Cortex-A710/X2 erratum 2224489.
921 Affected Cortex-A710/X2 cores might write to an out-of-range address, not reserved
924 (i.e., the TRBLIMITR_EL1.LIMIT), instead of wrapping around to the base.
926 Work around this in the driver by always making sure that there is a
932 …bool "Cortex-A510: Completion of affected memory accesses might not be guaranteed by completion of…
936 This option adds a workaround for ARM Cortex-A510 erratum #2441009.
938 Under very rare circumstances, affected Cortex-A510 CPUs
939 may not handle a race between a break-before-make sequence on one
940 CPU, and another CPU accessing the same page. This could allow a
943 Work around this by adding the affected CPUs to the list that needs
949 bool "Cortex-A510: 2064142: workaround TRBE register writes while disabled"
953 This option adds the workaround for ARM Cortex-A510 erratum 2064142.
955 Affected Cortex-A510 core might fail to write into system registers after the
958 and TRBTRG_EL1 will be ignored and will not be effected.
960 Work around this in the driver by executing TSB CSYNC and DSB after collection
961 is stopped and before performing a system register write to one of the affected
967 bool "Cortex-A510: 2038923: workaround TRBE corruption with enable"
971 This option adds the workaround for ARM Cortex-A510 erratum 2038923.
973 Affected Cortex-A510 core might cause an inconsistent view on whether trace is
977 execution changes from a context, in which trace is prohibited to one where it
978 isn't, or vice versa. In these mentioned conditions, the view of whether trace
979 is prohibited is inconsistent between parts of the CPU, and the trace buffer or
982 Work around this in the driver by preventing an inconsistent view of whether the
990 bool "Cortex-A510: 1902691: workaround TRBE trace corruption"
994 This option adds the workaround for ARM Cortex-A510 erratum 1902691.
996 Affected Cortex-A510 core might cause trace data corruption, when being written
997 into the memory. Effectively TRBE is broken and hence cannot be used to capture
1000 Work around this problem in the driver by just preventing TRBE initialization on
1008 bool "Cortex-A510: 2457168: workaround for AMEVCNTR01 incrementing incorrectly"
1012 This option adds the workaround for ARM Cortex-A510 erratum 2457168.
1015 as the system counter. On affected Cortex-A510 cores AMEVCNTR01 increments
1018 Work around this problem by returning 0 when reading the affected counter in
1019 key locations that results in disabling all users of this counter. This effect
1025 bool "Cortex-A715: 2645198: Workaround possible [ESR|FAR]_ELx corruption"
1028 This option adds the workaround for ARM Cortex-A715 erratum 2645198.
1030 If a Cortex-A715 cpu sees a page mapping permissions change from executable
1031 to non-executable, it may corrupt the ESR_ELx and FAR_ELx registers on the
1034 Only user-space does executable to non-executable permission transition via
1035 mprotect() system call. Workaround the problem by doing a break-before-make
1041 bool "Cortex-A520: 2966298: workaround for speculatively executed unprivileged load"
1044 This option adds the workaround for ARM Cortex-A520 erratum 2966298.
1046 On an affected Cortex-A520 core, a speculatively executed unprivileged
1049 Work around this problem by executing a TLBI before returning to EL0.
1057 Enable workaround for errata 22375 and 24313.
1059 This implements two gicv3-its errata workarounds for ThunderX. Both
1065 The fixes are in ITS initialization and basically ignore memory access
1066 type and table size provided by the TYPER and BASER registers.
1075 ITS SYNC command hang for cross node io and collections/cpu mapping.
1080 bool "Cavium errata 23154 and 38545: GICv3 lacks HW synchronisation"
1085 (access to icc_iar1_el1 is not sync'ed before and after).
1088 OcteonTX and OcteonTX2), resulting in deactivated interrupts being
1099 contains data for a non-current ASID. The fix is to
1105 bool "Cavium erratum 30115: Guest may disable interrupts in host"
1109 1.2, and T83 Pass 1.0, KVM guest execution may disable
1110 interrupts in host. Trapping both GICv3 group-0 and group-1
1116 bool "Cavium ThunderX2 erratum 219: PRFM between TTBR change and ISB fails"
1120 TTBR update and the corresponding context synchronizing operation can
1121 cause a spurious Data Abort to be delivered to any hardware thread in
1124 Work around the issue by avoiding the problematic code sequence and
1127 instruction and ensures context synchronization by virtue of the
1133 bool "Fujitsu-A64FX erratum E#010001: Undefined fault may occur wrongly"
1136 This option adds a workaround for Fujitsu-A64FX erratum E#010001.
1137 On some variants of the Fujitsu-A64FX cores ver(1.0, 1.1), memory
1141 case-1 TTBR0_EL1 with TCR_EL1.NFD0 == 1.
1142 case-2 TTBR0_EL2 with TCR_EL2.NFD0 == 1.
1143 case-3 TTBR1_EL1 with TCR_EL1.NFD1 == 1.
1144 case-4 TTBR1_EL2 with TCR_EL2.NFD1 == 1.
1146 The workaround is to ensure these bits are clear in TCR_ELx.
1147 The workaround only affects the Fujitsu-A64FX.
1156 when issued ITS commands such as VMOVP and VMAPP, and requires
1157 a 128kB offset to be applied to the target address in this commands.
1165 On Falkor v1, an incorrect ASID may be cached in the TLB when ASID
1166 and BADDR are changed together in TTBRx_EL1. Since we keep the ASID
1167 in TTBR1_EL1, this situation only occurs in the entry trampoline and
1168 then only for entries in the walk cache, since the leaf translation
1169 is unchanged. Work around the erratum by invalidating the walk cache
1207 If CNP is enabled on Carmel cores, non-sharable TLBIs on a core will not
1217 The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
1224 bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
1228 MSI doorbell writes with non-zero values for the device ID.
1256 allowing only two levels of page tables and faster TLB
1257 look-up. AArch32 emulation requires applications compiled
1270 a combination of page size and virtual address space size.
1273 bool "36-bit" if EXPERT
1277 bool "39-bit"
1281 bool "42-bit"
1285 bool "47-bit"
1289 bool "48-bit"
1292 bool "52-bit"
1295 Enable 52-bit virtual addressing for userspace when explicitly
1296 requested via a hint to mmap(). The kernel will also use 52-bit
1298 this feature is available, otherwise it reverts to 48-bit).
1300 NOTE: Enabling 52-bit virtual addressing in conjunction with
1301 ARMv8.3 Pointer Authentication will result in the PAC being
1303 impact on its susceptibility to brute-force attacks.
1305 If unsure, select 48-bit virtual addressing instead.
1310 bool "Force 52-bit virtual addresses for userspace"
1313 For systems with 52-bit userspace VAs enabled, the kernel will attempt
1314 to maintain compatibility with older software by providing 48-bit VAs
1317 This configuration option disables the 48-bit compatibility logic, and
1318 forces all userspace addresses to be 52-bit on HW that supports it. One
1339 bool "48-bit"
1342 bool "52-bit (ARMv8.2)"
1346 Enable support for a 52-bit physical address space, introduced as
1347 part of the ARMv8.2-LPA extension.
1350 do not support ARMv8.2-LPA, but with some added memory overhead (and
1365 applications will need to be compiled and linked for the endianness
1369 bool "Build big-endian kernel"
1372 Say Y if you plan on running a kernel with a big-endian userspace.
1375 bool "Build little-endian kernel"
1377 Say Y if you plan on running a kernel with a little-endian userspace.
1383 bool "Multi-core scheduler support"
1385 Multi-core scheduler support improves the CPU scheduler's decision
1386 making when dealing with multi-core CPU chips at a cost of slightly
1387 increased overhead in some places. If unsure say N here.
1395 by sharing mid-level caches, last-level cache tags or internal
1402 MultiThreading at a cost of slightly increased overhead in some
1406 int "Maximum number of CPUs (2-4096)"
1411 bool "Support for hot-pluggable CPUs"
1414 Say Y here to experiment with turning CPUs off and on. CPUs
1419 bool "NUMA Memory Allocation and Scheduler Support"
1428 Enable NUMA (Non-Uniform Memory Access) support.
1431 local memory of the CPU and add some more
1456 def_bool $(cc-option, -fsanitize=shadow-call-stack -ffixed-x18)
1470 accounting. Time spent executing other tasks in parallel with
1474 If in doubt, say N here.
1513 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
1519 # so the maximum value of MAX_ORDER is SECTION_SIZE_BITS - PAGE_SHIFT:
1522 # ----+-------------------+--------------+-----------------+--------------------+
1533 contiguous allocations. The limit is called MAX_ORDER and it
1547 bool "Unmap kernel when running in userspace (aka \"KAISER\")" if EXPERT
1550 Speculation attacks against some high-performance processors can
1551 be used to bypass MMU permission checks and leak kernel data to
1553 when running in userspace, mapping it back in on exception entry
1554 via a trampoline page in the vector table.
1562 Speculation attacks against some high-performance processors can
1564 When taking an exception from user-space, a sequence of branches
1571 Apply read-only attributes of VM areas to the linear alias of
1572 the backing pages as well. This prevents code or read-only data
1575 be turned off at runtime by passing rodata=[off|on] (and turned on
1579 which may adversely affect performance in some cases.
1585 user-space memory directly by pointing TTBR0_EL1 to a reserved
1586 zeroed area and reserved ASID. The user access routines
1593 When this option is enabled, user applications can opt in to a
1596 Documentation/arch/arm64/tagged-address-abi.rst.
1599 bool "Kernel support for 32-bit EL0"
1605 This option enables support for a 32-bit EL0 running under a 64-bit
1606 kernel at EL1. AArch32-specific components such as system calls,
1607 the user helper functions, VFP support and the ptrace interface are
1614 If you want to execute 32-bit userspace applications, say Y.
1619 bool "Enable kuser helpers page for 32-bit applications"
1622 Warning: disabling this option may break 32-bit user programs.
1625 helper code to userspace in read only form at a fixed location
1636 If all of the binaries and libraries which run on your platform
1637 are built specifically for your platform, and make no use of
1639 such exploits. However, in that case, if a binary or library
1646 bool "Enable vDSO for 32-bit applications"
1652 Place in the process address space of 32-bit applications an
1654 and clock_gettime.
1656 You must have a 32-bit build of glibc 2.22 or later for programs
1660 bool "Compile the 32-bit vDSO for Thumb-2 mode" if EXPERT
1664 Compile the compat vDSO with '-mthumb -fomit-frame-pointer' if y,
1665 otherwise with '-marm'.
1668 bool "Fix up misaligned multi-word loads and stores in user space"
1675 that have been deprecated or obsoleted in the architecture.
1693 In some older versions of glibc [<=2.8] SWP is used during futex
1710 The CP15 barrier instructions - CP15ISB, CP15DSB, and
1711 CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
1712 strongly recommended to use the ISB, DSB, and DMB
1726 The SETEND instruction alters the data-endianness of the
1727 AArch32 EL0, and is deprecated in ARMv8.
1734 for this feature to be enabled. If a new CPU - which doesn't support mixed
1735 endian - is hotplugged in after this feature has been enabled, there could
1736 be unexpected results in the applications.
1746 bool "Support for hardware updates of the Access and Dirty page flags"
1750 hardware updates of the access and dirty information in page
1751 table entries. When enabled in TCR_EL1 (HA and HD bits) on
1754 Similarly, writes to read-only pages with the DBM bit set will
1755 clear the read-only bit (AP[2]) instead of raising a
1759 to work on pre-ARMv8.1 hardware and the performance impact is
1767 prevents the kernel or hypervisor from accessing user-space (EL0)
1773 The feature is detected at runtime, and will remain as a 'nop'
1777 def_bool $(as-instr,.arch_extension lse)
1789 atomic instructions that are designed specifically to scale in
1792 Say Y here to make use of these instructions for the in-kernel
1794 not support these instructions and requires the kernel to be
1795 built with binutils >= 2.25 in order for the new instructions
1803 def_bool $(cc-option,-Wa$(comma)-march=armv8.2-a)
1806 def_bool $(as-instr,.arch armv8.2-a+sha3)
1816 The feature is detected at runtime, and the kernel will use DC CVAC
1824 CPUs that support the Reliability, Availability and Serviceability
1825 (RAS) Extensions, part of ARMv8.2 are able to track faults and
1826 errors, classify them and report them to software.
1829 barriers to determine if faults are pending and read the
1833 and access the new registers if the system supports the extension.
1842 be shared between different PEs in the same inner shareable
1844 caching of such entries in the TLB.
1847 at runtime, and does not affect PEs that do not implement
1859 instructions for signing and authenticating pointers against secret
1861 and other attacks.
1866 context-switched along with the process.
1868 The feature is detected at runtime. If the feature is not present in
1874 address auth and the late CPU has then the late CPU will still boot
1889 If the compiler supports the -mbranch-protection or
1890 -msign-return-address flag (e.g. GCC 7 or later), then this option
1892 protection. In this case, and if the target hardware is known to
1901 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf)
1905 def_bool $(cc-option,-msign-return-address=all)
1908 def_bool $(cc-option,-Wa$(comma)-march=armv8.3-a)
1911 def_bool $(as-instr,.cfi_startproc\n.cfi_negate_ra_state\n.cfi_endproc\n)
1914 def_bool $(as-instr,.arch_extension rcpc)
1932 extension. The required support is present in:
1933 * Version 1.5 and later of the ARM Trusted Firmware
1944 def_bool $(cc-option,-Wa$(comma)-march=armv8.4-a)
1951 ARMv8.4-TLBI provides TLBI invalidation instruction that apply to a
1954 The feature introduces new assembly instructions, and they were
1962 def_bool $(cc-option,-Wa$(comma)-march=armv8.5-a)
1996 # https://github.com/llvm/llvm-project/commit/a88c722e687e6780dcd6a58718350dc76fcc4cc9
2001 and enable enforcement of this for kernel code. When this option
2002 is enabled and the system supports BTI all kernel code including
2007 def_bool $(cc-option,-mbranch-protection=pac-ret+leaf+bti)
2014 that EL0 accesses made via TTBR1 always fault in constant time,
2016 with lower overhead and without disrupting legitimate access to
2022 # Initial support for MTE went in binutils 2.32.0, checked with
2023 # ".arch armv8.5-a+memtag" below. However, this was incomplete
2025 # is only supported in the newer 2.32.x and 2.33 binutils
2027 def_bool $(as-instr,.arch armv8.5-a+memtag\nstgm xzr$(comma)[x0])
2035 # Required for tag checking in the uaccess routines
2042 architectural support for run-time, always-on detection of
2044 to eliminate vulnerabilities arising from memory-unsafe
2052 not be allowed a late bring-up.
2055 explicitly opt in. The mechanism for the userspace is
2056 described in:
2058 Documentation/arch/arm64/memory-tagging-extension.rst.
2070 Access Never to be used with Execute-only mappings.
2072 The feature is detected at runtime, and will remain disabled
2081 execution state which complements and extends the SIMD functionality
2082 of the base architecture to support much larger vectors and to enable
2092 is present in:
2094 * version 1.5 and later of the ARM Trusted Firmware
2096 ("bootwrapper: SVE: Enable SVE for EL2 and below").
2101 If you need the kernel to boot on SVE-capable hardware with broken
2104 booting the kernel. If unsure and you are not observing these
2119 bool "Support for NMI-like interrupts"
2122 Adds support for mimicking Non-Maskable Interrupts through the use of
2165 random u64 value in /chosen/kaslr-seed at kernel entry.
2169 to the kernel proper. In addition, it will randomise the physical
2182 but it does imply that function calls between modules and the core
2183 kernel will need to be resolved via veneers in the module PLT.
2187 core kernel, so branch relocations are almost always in range unless
2188 the region is exhausted. In this particular case of region
2192 …def_bool $(cc-option,-mstack-protector-guard=sysreg -mstack-protector-guard-reg=sp_el0 -mstack-pro…
2217 protocol even if the corresponding data is present in the ACPI
2224 Provide a set of default command-line options at build time by
2238 Uses the command-line options passed by the boot loader. If
2240 string provided in CMDLINE will be used.
2248 command-line options your boot loader passes to the kernel.
2270 by UEFI firmware (such as non-volatile variables, realtime
2271 clock, and platform reset). A UEFI stub is also provided to
2284 continue to boot on existing non-UEFI platforms.