Lines Matching refs:invalidate
95 mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
98 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
127 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
153 2: mcr p15, 0, ip, c7, c14, 2 @ clean + invalidate D set/way
161 mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
181 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
182 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
184 mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
185 mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
221 mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
241 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
246 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
260 mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
284 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
351 1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
479 mcreq p15, 0, ip, c7, c5, 0 @ invalidate I cache
483 mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
523 mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
524 mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
537 mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
540 mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4