Lines Matching +full:read +full:- +full:1
1 /* SPDX-License-Identifier: GPL-2.0 */
3 * FILE SA-1100.h
9 * System StrongARM SA-1100
12 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
14 * StrongARM SA-1100 data sheet version 2.2.
21 #error You must include hardware.h not SA-1100.h
52 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
53 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
54 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
55 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
57 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
59 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
60 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
62 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
70 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
71 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
72 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
73 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
81 * Controller (UDC) Control Register (read/write).
83 * Controller (UDC) Address Register (read/write).
86 * (read/write).
89 * (read/write).
91 * Controller (UDC) Control/Status register end-point 0
92 * (read/write).
94 * Controller (UDC) Control/Status register end-point 1
95 * (output, read/write).
97 * Controller (UDC) Control/Status register end-point 2
98 * (input, read/write).
100 * Controller (UDC) Data register end-point 0
101 * (read/write).
103 * Controller (UDC) Write Count register end-point 0
104 * (read).
106 * Controller (UDC) Data Register (read/write).
108 * Controller (UDC) Status Register (read/write).
115 #define Ser0UDCCS0 __REG(0x80000010) /* Ser. port 0 UDC Control/Status reg. end-point 0 */
116 #define Ser0UDCCS1 __REG(0x80000014) /* Ser. port 0 UDC Control/Status reg. end-point 1 (output) */
117 #define Ser0UDCCS2 __REG(0x80000018) /* Ser. port 0 UDC Control/Status reg. end-point 2 (input) */
118 #define Ser0UDCD0 __REG(0x8000001C) /* Ser. port 0 UDC Data reg. end-point 0 */
119 #define Ser0UDCWC __REG(0x80000020) /* Ser. port 0 UDC Write Count reg. end-point 0 */
124 #define UDCCR_UDA 0x00000002 /* UDC Active (read) */
126 #define UDCCR_EIM 0x00000008 /* End-point 0 Interrupt Mask */
139 #define UDCOMP_OUTMAXP Fld (8, 0) /* OUTput MAXimum Packet size - 1 */
142 /* [1..256 byte] */ \
143 (((Size) - 1) << FShft (UDCOMP_OUTMAXP))
145 #define UDCIMP_INMAXP Fld (8, 0) /* INput MAXimum Packet size - 1 */
148 /* [1..256 byte] */ \
149 (((Size) - 1) << FShft (UDCIMP_INMAXP))
151 #define UDCCS0_OPR 0x00000001 /* Output Packet Ready (read) */
156 #define UDCCS0_SE 0x00000020 /* Setup End (read) */
161 #define UDCCS1_RFS 0x00000001 /* Receive FIFO 12-bytes or more */
162 /* Service request (read) */
164 #define UDCCS1_RPE 0x00000004 /* Receive Packet Error (read) */
167 #define UDCCS1_RNE 0x00000020 /* Receive FIFO Not Empty (read) */
169 #define UDCCS2_TFS 0x00000001 /* Transmit FIFO 8-bytes or less */
170 /* Service request (read) */
172 #define UDCCS2_TPE 0x00000004 /* Transmit Packet Error (read) */
173 #define UDCCS2_TUR 0x00000008 /* Transmit FIFO Under-Run */
183 #define UDCSR_EIR 0x00000001 /* End-point 0 Interrupt Request */
195 * Ser1UTCR0 Serial port 1 Universal Asynchronous
197 * (read/write).
198 * Ser1UTCR1 Serial port 1 Universal Asynchronous
199 * Receiver/Transmitter (UART) Control Register 1
200 * (read/write).
201 * Ser1UTCR2 Serial port 1 Universal Asynchronous
203 * (read/write).
204 * Ser1UTCR3 Serial port 1 Universal Asynchronous
206 * (read/write).
207 * Ser1UTDR Serial port 1 Universal Asynchronous
209 * (read/write).
210 * Ser1UTSR0 Serial port 1 Universal Asynchronous
212 * (read/write).
213 * Ser1UTSR1 Serial port 1 Universal Asynchronous
214 * Receiver/Transmitter (UART) Status Register 1 (read).
218 * (read/write).
220 * Receiver/Transmitter (UART) Control Register 1
221 * (read/write).
224 * (read/write).
227 * (read/write).
230 * (read/write).
233 * (read/write).
236 * (read/write).
238 * Receiver/Transmitter (UART) Status Register 1 (read).
242 * (read/write).
244 * Receiver/Transmitter (UART) Control Register 1
245 * (read/write).
248 * (read/write).
251 * (read/write).
254 * (read/write).
257 * (read/write).
259 * Receiver/Transmitter (UART) Status Register 1 (read).
267 #define _UTCR0(Nb) __REG(0x80010000 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 0 [1..3] */
268 #define _UTCR1(Nb) __REG(0x80010004 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 1 [1..3] */
269 #define _UTCR2(Nb) __REG(0x80010008 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 2 [1..3] */
270 #define _UTCR3(Nb) __REG(0x8001000C + ((Nb) - 1)*0x00020000) /* UART Control Reg. 3 [1..3] */
271 #define _UTCR4(Nb) __REG(0x80010010 + ((Nb) - 1)*0x00020000) /* UART Control Reg. 4 [2] */
272 #define _UTDR(Nb) __REG(0x80010014 + ((Nb) - 1)*0x00020000) /* UART Data Reg. [1..3] */
273 #define _UTSR0(Nb) __REG(0x8001001C + ((Nb) - 1)*0x00020000) /* UART Status Reg. 0 [1..3] */
274 #define _UTSR1(Nb) __REG(0x80010020 + ((Nb) - 1)*0x00020000) /* UART Status Reg. 1 [1..3] */
276 #define Ser1UTCR0 _UTCR0 (1) /* Ser. port 1 UART Control Reg. 0 */
277 #define Ser1UTCR1 _UTCR1 (1) /* Ser. port 1 UART Control Reg. 1 */
278 #define Ser1UTCR2 _UTCR2 (1) /* Ser. port 1 UART Control Reg. 2 */
279 #define Ser1UTCR3 _UTCR3 (1) /* Ser. port 1 UART Control Reg. 3 */
280 #define Ser1UTDR _UTDR (1) /* Ser. port 1 UART Data Reg. */
281 #define Ser1UTSR0 _UTSR0 (1) /* Ser. port 1 UART Status Reg. 0 */
282 #define Ser1UTSR1 _UTSR1 (1) /* Ser. port 1 UART Status Reg. 1 */
285 #define Ser2UTCR1 _UTCR1 (2) /* Ser. port 2 UART Control Reg. 1 */
291 #define Ser2UTSR1 _UTSR1 (2) /* Ser. port 2 UART Status Reg. 1 */
294 #define Ser3UTCR1 _UTCR1 (3) /* Ser. port 3 UART Control Reg. 1 */
299 #define Ser3UTSR1 _UTSR1 (3) /* Ser. port 3 UART Status Reg. 1 */
318 #define UTCR0_EvenPar (UTCR0_OES*1) /* Even Parity */
320 #define UTCR0_1StpBit (UTCR0_SBS*0) /* 1 Stop Bit per frame */
321 #define UTCR0_2StpBit (UTCR0_SBS*1) /* 2 Stop Bits per frame */
323 #define UTCR0_7BitData (UTCR0_DSS*0) /* 7-Bit Data */
324 #define UTCR0_8BitData (UTCR0_DSS*1) /* 8-Bit Data */
326 /* (ser. port 1: GPIO [18], */
329 #define UTCR0_RcRsEdg (UTCR0_RCE*0) /* Receive clock Rising-Edge */
330 #define UTCR0_RcFlEdg (UTCR0_RCE*1) /* Receive clock Falling-Edge */
332 #define UTCR0_TrRsEdg (UTCR0_TCE*0) /* Transmit clock Rising-Edge */
333 #define UTCR0_TrFlEdg (UTCR0_TCE*1) /* Transmit clock Falling-Edge */
337 #define UTCR1_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
338 #define UTCR2_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
339 /* fua = fxtl/(16*(BRD[11:0] + 1)) */
340 /* Tua = 16*(BRD [11:0] + 1)*Txtl */
342 (((Div) - 16)/16 >> FSize (UTCR2_BRD) << \
345 (((Div) - 16)/16 & FAlnMsk (UTCR2_BRD) << \
350 (((Div) - 1)/16 >> FSize (UTCR2_BRD) << \
353 (((Div) - 1)/16 & FAlnMsk (UTCR2_BRD) << \
361 #define UTCR3_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
363 #define UTCR3_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
365 #define UTCR3_LBM 0x00000020 /* Look-Back Mode */
370 #define UTCR4_HSE 0x00000001 /* Hewlett-Packard Serial InfraRed */
371 /* (HP-SIR) modulation Enable */
372 #define UTCR4_NRZ (UTCR4_HSE*0) /* Non-Return to Zero modulation */
373 #define UTCR4_HPSIR (UTCR4_HSE*1) /* HP-SIR modulation */
374 #define UTCR4_LPM 0x00000002 /* Low-Power Mode */
376 #define UTCR4_Z1_6us (UTCR4_LPM*1) /* Zero pulse = 1.6 us */
380 #define UTDR_PRE 0x00000100 /* receive PaRity Error (read) */
381 #define UTDR_FRE 0x00000200 /* receive FRaming Error (read) */
382 #define UTDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
385 #define UTSR0_TFS 0x00000001 /* Transmit FIFO 1/2-full or less */
386 /* Service request (read) */
387 #define UTSR0_RFS 0x00000002 /* Receive FIFO 1/3-to-2/3-full or */
388 /* more Service request (read) */
392 #define UTSR0_EIF 0x00000020 /* Error In FIFO (read) */
394 #define UTSR1_TBY 0x00000001 /* Transmitter BusY (read) */
395 #define UTSR1_RNE 0x00000002 /* Receive FIFO Not Empty (read) */
396 #define UTSR1_TNF 0x00000004 /* Transmit FIFO Not Full (read) */
397 #define UTSR1_PRE 0x00000008 /* receive PaRity Error (read) */
398 #define UTSR1_FRE 0x00000010 /* receive FRaming Error (read) */
399 #define UTSR1_ROR 0x00000020 /* Receive FIFO Over-Run (read) */
406 * Ser1SDCR0 Serial port 1 Synchronous Data Link Controller (SDLC)
407 * Control Register 0 (read/write).
408 * Ser1SDCR1 Serial port 1 Synchronous Data Link Controller (SDLC)
409 * Control Register 1 (read/write).
410 * Ser1SDCR2 Serial port 1 Synchronous Data Link Controller (SDLC)
411 * Control Register 2 (read/write).
412 * Ser1SDCR3 Serial port 1 Synchronous Data Link Controller (SDLC)
413 * Control Register 3 (read/write).
414 * Ser1SDCR4 Serial port 1 Synchronous Data Link Controller (SDLC)
415 * Control Register 4 (read/write).
416 * Ser1SDDR Serial port 1 Synchronous Data Link Controller (SDLC)
417 * Data Register (read/write).
418 * Ser1SDSR0 Serial port 1 Synchronous Data Link Controller (SDLC)
419 * Status Register 0 (read/write).
420 * Ser1SDSR1 Serial port 1 Synchronous Data Link Controller (SDLC)
421 * Status Register 1 (read/write).
429 #define Ser1SDCR0 __REG(0x80020060) /* Ser. port 1 SDLC Control Reg. 0 */
430 #define Ser1SDCR1 __REG(0x80020064) /* Ser. port 1 SDLC Control Reg. 1 */
431 #define Ser1SDCR2 __REG(0x80020068) /* Ser. port 1 SDLC Control Reg. 2 */
432 #define Ser1SDCR3 __REG(0x8002006C) /* Ser. port 1 SDLC Control Reg. 3 */
433 #define Ser1SDCR4 __REG(0x80020070) /* Ser. port 1 SDLC Control Reg. 4 */
434 #define Ser1SDDR __REG(0x80020078) /* Ser. port 1 SDLC Data Reg. */
435 #define Ser1SDSR0 __REG(0x80020080) /* Ser. port 1 SDLC Status Reg. 0 */
436 #define Ser1SDSR1 __REG(0x80020084) /* Ser. port 1 SDLC Status Reg. 1 */
440 #define SDCR0_UART (SDCR0_SUS*1) /* UART mode (TXD1 & RXD1) */
443 #define SDCR0_DblFlg (SDCR0_SDF*1) /* Double start Flag */
444 #define SDCR0_LBM 0x00000004 /* Look-Back Mode */
447 #define SDCR0_NRZ (SDCR0_BMS*1) /* Non-Return to Zero modulation */
452 #define SDCR0_SClkOut (SDCR0_SCD*1) /* Sample Clock Output */
454 #define SDCR0_RcRsEdg (SDCR0_RCE*0) /* Receive clock Rising-Edge */
455 #define SDCR0_RcFlEdg (SDCR0_RCE*1) /* Receive clock Falling-Edge */
457 #define SDCR0_TrRsEdg (SDCR0_TCE*0) /* Transmit clock Rising-Edge */
458 #define SDCR0_TrFlEdg (SDCR0_TCE*1) /* Transmit clock Falling-Edge */
464 #define SDCR1_RIE 0x00000008 /* Receive FIFO 1/3-to-2/3-full or */
466 #define SDCR1_TIE 0x00000010 /* Transmit FIFO 1/2-full or less */
469 #define SDCR1_TUS 0x00000040 /* Transmit FIFO Under-run Select */
470 #define SDCR1_EFrmURn (SDCR1_TUS*0) /* End Frame on Under-Run */
471 #define SDCR1_AbortURn (SDCR1_TUS*1) /* Abort on Under-Run */
476 #define SDCR3_BRD Fld (4, 0) /* Baud Rate Divisor/16 - 1 [11:8] */
477 #define SDCR4_BRD Fld (8, 0) /* Baud Rate Divisor/16 - 1 [7:0] */
478 /* fsd = fxtl/(16*(BRD[11:0] + 1)) */
479 /* Tsd = 16*(BRD[11:0] + 1)*Txtl */
481 (((Div) - 16)/16 >> FSize (SDCR4_BRD) << \
484 (((Div) - 16)/16 & FAlnMsk (SDCR4_BRD) << \
489 (((Div) - 1)/16 >> FSize (SDCR4_BRD) << \
492 (((Div) - 1)/16 & FAlnMsk (SDCR4_BRD) << \
499 #define SDDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
500 #define SDDR_CRE 0x00000200 /* receive CRC Error (read) */
501 #define SDDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
504 #define SDSR0_EIF 0x00000001 /* Error In FIFO (read) */
505 #define SDSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
507 #define SDSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
508 /* Service request (read) */
509 #define SDSR0_RFS 0x00000010 /* Receive FIFO 1/3-to-2/3-full or */
510 /* more Service request (read) */
512 #define SDSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
513 #define SDSR1_TBY 0x00000002 /* Transmitter BusY (read) */
514 #define SDSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
515 #define SDSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
517 #define SDSR1_EOF 0x00000020 /* receive End-Of-Frame (read) */
518 #define SDSR1_CRE 0x00000040 /* receive CRC Error (read) */
519 #define SDSR1_ROR 0x00000080 /* Receive FIFO Over-Run (read) */
523 * High-Speed Serial to Parallel controller (HSSP) control registers
526 * Ser2HSCR0 Serial port 2 High-Speed Serial to Parallel
527 * controller (HSSP) Control Register 0 (read/write).
528 * Ser2HSCR1 Serial port 2 High-Speed Serial to Parallel
529 * controller (HSSP) Control Register 1 (read/write).
530 * Ser2HSDR Serial port 2 High-Speed Serial to Parallel
531 * controller (HSSP) Data Register (read/write).
532 * Ser2HSSR0 Serial port 2 High-Speed Serial to Parallel
533 * controller (HSSP) Status Register 0 (read/write).
534 * Ser2HSSR1 Serial port 2 High-Speed Serial to Parallel
535 * controller (HSSP) Status Register 1 (read).
536 * Ser2HSCR2 Serial port 2 High-Speed Serial to Parallel
537 * controller (HSSP) Control Register 2 (read/write).
540 * SA-1100.]
544 #define Ser2HSCR1 __REG(0x80040064) /* Ser. port 2 HSSP Control Reg. 1 */
547 #define Ser2HSSR1 __REG(0x80040078) /* Ser. port 2 HSSP Status Reg. 1 */
552 #define HSCR0_HSSP (HSCR0_ITR*1) /* HSSP mode (4 Mb/s) */
553 #define HSCR0_LBM 0x00000002 /* Look-Back Mode */
554 #define HSCR0_TUS 0x00000004 /* Transmit FIFO Under-run Select */
555 #define HSCR0_EFrmURn (HSCR0_TUS*0) /* End Frame on Under-Run */
556 #define HSCR0_AbortURn (HSCR0_TUS*1) /* Abort on Under-Run */
559 #define HSCR0_RIE 0x00000020 /* Receive FIFO 2/5-to-3/5-full or */
561 #define HSCR0_TIE 0x00000040 /* Transmit FIFO 1/2-full or less */
569 #define HSDR_EOF 0x00000100 /* receive End-Of-Frame (read) */
570 #define HSDR_CRE 0x00000200 /* receive CRC Error (read) */
571 #define HSDR_ROR 0x00000400 /* Receive FIFO Over-Run (read) */
574 #define HSSR0_EIF 0x00000001 /* Error In FIFO (read) */
575 #define HSSR0_TUR 0x00000002 /* Transmit FIFO Under-Run */
577 #define HSSR0_TFS 0x00000008 /* Transmit FIFO 1/2-full or less */
578 /* Service request (read) */
579 #define HSSR0_RFS 0x00000010 /* Receive FIFO 2/5-to-3/5-full or */
580 /* more Service request (read) */
583 #define HSSR1_RSY 0x00000001 /* Receiver SYnchronized (read) */
584 #define HSSR1_TBY 0x00000002 /* Transmitter BusY (read) */
585 #define HSSR1_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
586 #define HSSR1_TNF 0x00000008 /* Transmit FIFO Not Full (read) */
587 #define HSSR1_EOF 0x00000010 /* receive End-Of-Frame (read) */
588 #define HSSR1_CRE 0x00000020 /* receive CRC Error (read) */
589 #define HSSR1_ROR 0x00000040 /* Receive FIFO Over-Run (read) */
594 #define HSCR2_TrDataH (HSCR2_TXP*1) /* Transmit Data active High */
595 /* (non-inverted) */
599 #define HSCR2_RcDataH (HSCR2_RXP*1) /* Receive Data active High */
600 /* (non-inverted) */
604 * Multi-media Communications Port (MCP) control registers
607 * Ser4MCCR0 Serial port 4 Multi-media Communications Port (MCP)
608 * Control Register 0 (read/write).
609 * Ser4MCDR0 Serial port 4 Multi-media Communications Port (MCP)
610 * Data Register 0 (audio, read/write).
611 * Ser4MCDR1 Serial port 4 Multi-media Communications Port (MCP)
612 * Data Register 1 (telecom, read/write).
613 * Ser4MCDR2 Serial port 4 Multi-media Communications Port (MCP)
614 * Data Register 2 (CODEC registers, read/write).
615 * Ser4MCSR Serial port 4 Multi-media Communications Port (MCP)
616 * Status Register (read/write).
617 * Ser4MCCR1 Serial port 4 Multi-media Communications Port (MCP)
618 * Control Register 1 (read/write).
621 * SA-1100.]
632 #define Ser4MCDR1 __REG(0x8006000C) /* Ser. port 4 MCP Data Reg. 1 (telecom) */
635 #define Ser4MCCR1 __REG(0x90060030) /* Ser. port 4 MCP Control Reg. 1 */
666 #define MCCR0_ExtClk (MCCR0_ECS*1) /* External Clock (GPIO [21]) */
670 #define MCCR0_SmpCnt (MCCR0_ADM*1) /* Sampling Counter storing mode */
671 #define MCCR0_TTE 0x00080000 /* Telecom Transmit FIFO 1/2-full */
673 #define MCCR0_TRE 0x00100000 /* Telecom Receive FIFO 1/2-full */
675 #define MCCR0_ATE 0x00200000 /* Audio Transmit FIFO 1/2-full */
677 #define MCCR0_ARE 0x00400000 /* Audio Receive FIFO 1/2-full or */
679 #define MCCR0_LBM 0x00800000 /* Look-Back Mode */
680 #define MCCR0_ECP Fld (2, 24) /* External Clock Prescaler - 1 */
681 #define MCCR0_ExtClkDiv(Div) /* External Clock Divisor [1..4] */ \
682 (((Div) - 1) << FShft (MCCR0_ECP))
693 #define MCDR2_RW 0x00010000 /* reg. Read/Write (transmit) */
694 #define MCDR2_Rd (MCDR2_RW*0) /* reg. Read */
695 #define MCDR2_Wr (MCDR2_RW*1) /* reg. Write */
698 #define MCSR_ATS 0x00000001 /* Audio Transmit FIFO 1/2-full */
699 /* or less Service request (read) */
700 #define MCSR_ARS 0x00000002 /* Audio Receive FIFO 1/2-full or */
701 /* more Service request (read) */
702 #define MCSR_TTS 0x00000004 /* Telecom Transmit FIFO 1/2-full */
703 /* or less Service request (read) */
704 #define MCSR_TRS 0x00000008 /* Telecom Receive FIFO 1/2-full */
705 /* or more Service request (read) */
706 #define MCSR_ATU 0x00000010 /* Audio Transmit FIFO Under-run */
707 #define MCSR_ARO 0x00000020 /* Audio Receive FIFO Over-run */
708 #define MCSR_TTU 0x00000040 /* Telecom Transmit FIFO Under-run */
709 #define MCSR_TRO 0x00000080 /* Telecom Receive FIFO Over-run */
711 /* (read) */
713 /* (read) */
715 /* (read) */
717 /* (read) */
719 /* (read) */
720 #define MCSR_CRC 0x00002000 /* CODEC register Read Completed */
721 /* (read) */
722 #define MCSR_ACE 0x00004000 /* Audio CODEC Enabled (read) */
723 #define MCSR_TCE 0x00008000 /* Telecom CODEC Enabled (read) */
728 #define MCCR1_F10MHz (MCCR1_CFS*1) /* Freq. (fmc) = ~ 10 MHz */
737 * Register 0 (read/write).
739 * Register 1 (read/write).
741 * (rev. = 8) and higher of the StrongARM SA-1100.]
743 * Register (read/write).
745 * Register (read/write).
754 #define Ser4SSCR1 __REG(0x80070064) /* Ser. port 4 SSP Control Reg. 1 */
758 #define SSCR0_DSS Fld (4, 0) /* Data Size - 1 Select [3..15] */
760 (((Size) - 1) << FShft (SSCR0_DSS))
767 (1 << FShft (SSCR0_FRF))
771 #define SSCR0_SCR Fld (8, 8) /* Serial Clock Rate divisor/2 - 1 */
772 /* fss = fxtl/(2*(SCR + 1)) */
773 /* Tss = 2*(SCR + 1)*Txtl */
775 (((Div) - 2)/2 << FShft (SSCR0_SCR))
779 (((Div) - 1)/2 << FShft (SSCR0_SCR))
783 #define SSCR1_RIE 0x00000001 /* Receive FIFO 1/2-full or more */
785 #define SSCR1_TIE 0x00000002 /* Transmit FIFO 1/2-full or less */
787 #define SSCR1_LBM 0x00000004 /* Look-Back Mode */
790 #define SSCR1_SClkIactH (SSCR1_SPO*1) /* Sample Clock Inactive High */
792 #define SSCR1_SClk1P (SSCR1_SP*0) /* Sample Clock active 1 Period */
793 /* after frame (SFRM, 1st edge) */
794 #define SSCR1_SClk1_2P (SSCR1_SP*1) /* Sample Clock active 1/2 Period */
795 /* after frame (SFRM, 1st edge) */
798 #define SSCR1_ExtClk (SSCR1_ECS*1) /* External Clock (GPIO [19]) */
802 #define SSSR_TNF 0x00000002 /* Transmit FIFO Not Full (read) */
803 #define SSSR_RNE 0x00000004 /* Receive FIFO Not Empty (read) */
804 #define SSSR_BSY 0x00000008 /* SSP BuSY (read) */
805 #define SSSR_TFS 0x00000010 /* Transmit FIFO 1/2-full or less */
806 /* Service request (read) */
807 #define SSSR_RFS 0x00000020 /* Receive FIFO 1/2-full or more */
808 /* Service request (read) */
809 #define SSSR_ROR 0x00000040 /* Receive FIFO Over-Run */
817 * (read/write).
818 * OSMR1 Operating System (OS) timer Match Register 1
819 * (read/write).
821 * (read/write).
823 * (read/write).
825 * (read/write).
827 * (read/write).
828 * OWER Operating System (OS) timer Watch-dog Enable Register
829 * (read/write).
831 * (read/write).
835 #define OSMR1 io_p2v(0x90000004) /* OS timer Match Reg. 1 */
840 #define OWER io_p2v(0x90000018) /* OS timer Watch-dog Enable Reg. */
846 #define OSSR_M1 OSSR_M (1) /* Match detected 1 */
850 #define OWER_WME 0x00000001 /* Watch-dog Match Enable */
856 #define OIER_E1 OIER_E (1) /* match interrupt Enable 1 */
865 * PMCR Power Manager (PM) Control Register (read/write).
866 * PSSR Power Manager (PM) Sleep Status Register (read/write).
867 * PSPR Power Manager (PM) Scratch-Pad Register (read/write).
868 * PWER Power Manager (PM) Wake-up Enable Register
869 * (read/write).
871 * (read/write).
872 * PPCR Power Manager (PM) Phase-Locked Loop (PLL)
873 * Configuration Register (read/write).
874 * PGSR Power Manager (PM) General-Purpose Input/Output (GPIO)
875 * Sleep state Register (read/write, see GPIO pins).
876 * POSR Power Manager (PM) Oscillator Status Register (read).
886 #define PSPR __REG(0x90020008) /* PM Scratch-Pad Reg. */
887 #define PWER __REG(0x9002000C) /* PM Wake-up Enable Reg. */
902 #define PWER_GPIO(Nb) GPIO_GPIO (Nb) /* GPIO [0..27] wake-up enable */
903 #define PWER_GPIO0 PWER_GPIO (0) /* GPIO [0] wake-up enable */
904 #define PWER_GPIO1 PWER_GPIO (1) /* GPIO [1] wake-up enable */
905 #define PWER_GPIO2 PWER_GPIO (2) /* GPIO [2] wake-up enable */
906 #define PWER_GPIO3 PWER_GPIO (3) /* GPIO [3] wake-up enable */
907 #define PWER_GPIO4 PWER_GPIO (4) /* GPIO [4] wake-up enable */
908 #define PWER_GPIO5 PWER_GPIO (5) /* GPIO [5] wake-up enable */
909 #define PWER_GPIO6 PWER_GPIO (6) /* GPIO [6] wake-up enable */
910 #define PWER_GPIO7 PWER_GPIO (7) /* GPIO [7] wake-up enable */
911 #define PWER_GPIO8 PWER_GPIO (8) /* GPIO [8] wake-up enable */
912 #define PWER_GPIO9 PWER_GPIO (9) /* GPIO [9] wake-up enable */
913 #define PWER_GPIO10 PWER_GPIO (10) /* GPIO [10] wake-up enable */
914 #define PWER_GPIO11 PWER_GPIO (11) /* GPIO [11] wake-up enable */
915 #define PWER_GPIO12 PWER_GPIO (12) /* GPIO [12] wake-up enable */
916 #define PWER_GPIO13 PWER_GPIO (13) /* GPIO [13] wake-up enable */
917 #define PWER_GPIO14 PWER_GPIO (14) /* GPIO [14] wake-up enable */
918 #define PWER_GPIO15 PWER_GPIO (15) /* GPIO [15] wake-up enable */
919 #define PWER_GPIO16 PWER_GPIO (16) /* GPIO [16] wake-up enable */
920 #define PWER_GPIO17 PWER_GPIO (17) /* GPIO [17] wake-up enable */
921 #define PWER_GPIO18 PWER_GPIO (18) /* GPIO [18] wake-up enable */
922 #define PWER_GPIO19 PWER_GPIO (19) /* GPIO [19] wake-up enable */
923 #define PWER_GPIO20 PWER_GPIO (20) /* GPIO [20] wake-up enable */
924 #define PWER_GPIO21 PWER_GPIO (21) /* GPIO [21] wake-up enable */
925 #define PWER_GPIO22 PWER_GPIO (22) /* GPIO [22] wake-up enable */
926 #define PWER_GPIO23 PWER_GPIO (23) /* GPIO [23] wake-up enable */
927 #define PWER_GPIO24 PWER_GPIO (24) /* GPIO [24] wake-up enable */
928 #define PWER_GPIO25 PWER_GPIO (25) /* GPIO [25] wake-up enable */
929 #define PWER_GPIO26 PWER_GPIO (26) /* GPIO [26] wake-up enable */
930 #define PWER_GPIO27 PWER_GPIO (27) /* GPIO [27] wake-up enable */
931 #define PWER_RTC 0x80000000 /* RTC alarm wake-up enable */
933 #define PCFR_OPDE 0x00000001 /* Oscillator Power-Down Enable */
935 #define PCFR_ClkStp (PCFR_OPDE*1) /* Clock Stopped in sleep mode */
937 #define PCFR_PCMCIANeg (PCFR_FP*0) /* PCMCIA pins Negated (1) */
938 #define PCFR_PCMCIAFlt (PCFR_FP*1) /* PCMCIA pins Floating */
940 #define PCFR_StMemNeg (PCFR_FS*0) /* Static Memory pins Negated (1) */
941 #define PCFR_StMemFlt (PCFR_FS*1) /* Static Memory pins Floating */
1021 * (read/write).
1022 * RCSR Reset Controller (RC) Status Register (read/write).
1032 #define RCSR_WDR 0x00000004 /* Watch-Dog Reset */
1033 #define RCSR_SMR 0x00000008 /* Sleep-Mode Reset */
1040 * TUCR Test Unit Control Register (read/write).
1052 #define TUCR_MBGPIO (TUCR_MR*1) /* Memory Bus request (MBREQ) & */
1063 (1 << FShft (TUCR_TSEL))
1081 * General-Purpose Input/Output (GPIO) control registers
1084 * GPLR General-Purpose Input/Output (GPIO) Pin Level
1085 * Register (read).
1086 * GPDR General-Purpose Input/Output (GPIO) Pin Direction
1087 * Register (read/write).
1088 * GPSR General-Purpose Input/Output (GPIO) Pin output Set
1090 * GPCR General-Purpose Input/Output (GPIO) Pin output Clear
1092 * GRER General-Purpose Input/Output (GPIO) Rising-Edge
1093 * detect Register (read/write).
1094 * GFER General-Purpose Input/Output (GPIO) Falling-Edge
1095 * detect Register (read/write).
1096 * GEDR General-Purpose Input/Output (GPIO) Edge Detect
1097 * status Register (read/write).
1098 * GAFR General-Purpose Input/Output (GPIO) Alternate
1099 * Function Register (read/write).
1109 #define GRER __REG(0x90040010) /* GPIO Rising-Edge detect Reg. */
1110 #define GFER __REG(0x90040014) /* GPIO Falling-Edge detect Reg. */
1120 #define GPIO_GPIO1 GPIO_GPIO (1) /* GPIO [1] */
1149 GPIO_GPIO ((Nb) - 6)
1163 /* ser. port 1: */
1168 #define GPIO_UART_SCLK1 GPIO_GPIO (18) /* UART Sample CLocK 1 (I) */
1181 #define GPIO_1Hz GPIO_GPIO (25) /* 1 Hz clock (O) */
1186 #define GPDR_Out 1 /* Output */
1194 * Pending register (read).
1195 * ICMR Interrupt Controller (IC) Mask Register (read/write).
1196 * ICLR Interrupt Controller (IC) Level Register (read/write).
1198 * (read/write).
1200 * (rev. = 8) and higher of the StrongARM SA-1100.]
1202 * (FIQ) Pending register (read).
1203 * ICPR Interrupt Controller (IC) Pending Register (read).
1205 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1206 * StrongARM SA-1100, it is active high (non-inverted) in
1220 #define IC_GPIO1 IC_GPIO (1) /* GPIO [1] */
1233 #define IC_Ser1SDLC 0x00004000 /* Ser. port 1 SDLC */
1234 #define IC_Ser1UART 0x00008000 /* Ser. port 1 UART */
1242 #define IC_DMA1 IC_DMA (1) /* DMA controller channel 1 */
1250 #define IC_OST1 IC_OST (1) /* OS Timer match 1 */
1253 #define IC_RTC1Hz 0x40000000 /* RTC 1 Hz clock */
1257 #define ICLR_FIQ 1 /* Fast Interrupt reQuest */
1259 #define ICCR_DIM 0x00000001 /* Disable Idle-mode interrupt */
1261 #define ICCR_IdleAllInt (ICCR_DIM*0) /* Idle-mode All Interrupt enable */
1263 #define ICCR_IdleMskInt (ICCR_DIM*1) /* Idle-mode non-Masked Interrupt */
1272 * Register (read/write).
1274 * (read/write).
1276 * Register (read/write).
1277 * PSDR Peripheral Pin Controller (PPC) Sleep-mode pin
1278 * Direction Register (read/write).
1280 * (read).
1286 #define PSDR __REG(0x9006000C) /* PPC Sleep-mode pin Direction Reg. */
1292 #define PPC_LDD1 PPC_LDD (1) /* LCD Data [1] */
1303 /* ser. port 1: */
1304 #define PPC_TXD1 0x00001000 /* SDLC/UART Transmit Data 1 */
1305 #define PPC_RXD1 0x00002000 /* SDLC/UART Receive Data 1 */
1319 #define PPDR_Out 1 /* Output */
1321 /* ser. port 1: */
1324 #define PPAR_UARTGPIO (PPAR_UPR*1) /* UART on GPIO [14:15] */
1329 #define PPAR_SSPGPIO (PPAR_SPR*1) /* SSP on GPIO [10:13] */
1332 #define PSDR_Flt 1 /* Floating (input) in sleep mode */
1335 #define PPFR_SP1TX 0x00001000 /* Ser. Port 1 SDLC/UART Transmit */
1336 #define PPFR_SP1RX 0x00002000 /* Ser. Port 1 SDLC/UART Receive */
1343 #define PPFR_PPCEn 1 /* PPC Enabled */
1347 * Dynamic Random-Access Memory (DRAM) control registers
1350 * MDCNFG Memory system: Dynamic Random-Access Memory (DRAM)
1351 * CoNFiGuration register (read/write).
1352 * MDCAS0 Memory system: Dynamic Random-Access Memory (DRAM)
1354 * (read/write).
1355 * MDCAS1 Memory system: Dynamic Random-Access Memory (DRAM)
1356 * Column Address Strobe (CAS) shift register 1
1357 * (read/write).
1358 * MDCAS2 Memory system: Dynamic Random-Access Memory (DRAM)
1360 * (read/write).
1370 #define MDCAS1 __REG(0xA0000008) /* DRAM CAS shift reg. 1 */
1377 #define MDCNFG_DE1 MDCNFG_DE (1) /* DRAM Enable bank 1 */
1380 #define MDCNFG_DRAC Fld (2, 4) /* DRAM Row Address Count - 9 */
1382 (((Add) - 9) << FShft (MDCNFG_DRAC))
1385 #define MDCNFG_TRP Fld (4, 7) /* Time RAS Pre-charge - 1 [Tmem] */
1386 #define MDCNFG_PrChrg(Tcpu) /* Pre-Charge time [2..32 Tcpu] */ \
1387 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRP))
1389 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRP))
1390 #define MDCNFG_TRASR Fld (4, 11) /* Time RAS Refresh - 1 [Tmem] */
1392 (((Tcpu) - 2)/2 << FShft (MDCNFG_TRASR))
1394 (((Tcpu) - 1)/2 << FShft (MDCNFG_TRASR))
1406 #define MDCNFG_SA1110_DE1 0x00000002 /* DRAM Enable bank 1 */
1407 #define MDCNFG_SA1110_DTIM0 0x00000004 /* DRAM timing type 0/1 */
1408 #define MDCNFG_SA1110_DWID0 0x00000008 /* DRAM bus width 0/1 */
1410 /* bank 0/1 */
1411 #define MDCNFG_SA1110_CDB20 0x00000080 /* Mem Clock divide by 2 0/1 */
1412 #define MDCNFG_SA1110_TRP0 Fld(3, 8) /* RAS precharge 0/1 */
1414 /* deassertion 0/1 */
1415 #define MDCNFG_SA1110_TWR0 Fld(2, 14) /* SDRAM write recovery 0/1 */
1417 #define MDCNFG_SA1110_DE3 0x00020000 /* DRAM Enable bank 1 */
1418 #define MDCNFG_SA1110_DTIM2 0x00040000 /* DRAM timing type 0/1 */
1419 #define MDCNFG_SA1110_DWID2 0x00080000 /* DRAM bus width 0/1 */
1421 /* bank 0/1 */
1422 #define MDCNFG_SA1110_CDB22 0x00800000 /* Mem Clock divide by 2 0/1 */
1423 #define MDCNFG_SA1110_TRP2 Fld(3, 24) /* RAS precharge 0/1 */
1425 /* deassertion 0/1 */
1426 #define MDCNFG_SA1110_TWR2 Fld(2, 30) /* SDRAM write recovery 0/1 */
1434 * (read/write).
1435 * MSC1 Memory system: Static memory Control register 1
1436 * (read/write).
1444 #define MSC1 __REG(0xa0000014) /* Static memory Control reg. 1 */
1450 #define MSC0_Bnk1 MSC_Bnk (1) /* static memory Bank 1 */
1455 #define MSC_NonBrst /* Non-Burst static memory */ \
1457 #define MSC_SRAM /* 32-bit byte-writable SRAM */ \
1458 (1 << FShft (MSC_RT))
1459 #define MSC_Brst4 /* Burst-of-4 static memory */ \
1461 #define MSC_Brst8 /* Burst-of-8 static memory */ \
1464 #define MSC_32BitStMem (MSC_RBW*0) /* 32-Bit Static Memory */
1465 #define MSC_16BitStMem (MSC_RBW*1) /* 16-Bit Static Memory */
1466 #define MSC_RDF Fld (5, 3) /* ROM/static memory read Delay */
1467 /* First access - 1(.5) [Tmem] */
1468 #define MSC_1stRdAcc(Tcpu) /* 1st Read Access time (burst */ \
1470 ((((Tcpu) - 3)/2) << FShft (MSC_RDF))
1471 #define MSC_Ceil1stRdAcc(Tcpu) /* Ceil. of 1stRdAcc [3..65 Tcpu] */ \
1472 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1473 #define MSC_RdAcc(Tcpu) /* Read Access time (non-burst */ \
1475 ((((Tcpu) - 2)/2) << FShft (MSC_RDF))
1477 ((((Tcpu) - 1)/2) << FShft (MSC_RDF))
1478 #define MSC_RDN Fld (5, 8) /* ROM/static memory read Delay */
1479 /* Next access - 1 [Tmem] */
1480 #define MSC_NxtRdAcc(Tcpu) /* Next Read Access time (burst */ \
1482 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1484 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1485 #define MSC_WrAcc(Tcpu) /* Write Access time (non-burst */ \
1487 ((((Tcpu) - 2)/2) << FShft (MSC_RDN))
1489 ((((Tcpu) - 1)/2) << FShft (MSC_RDN))
1504 * Configuration Register (read/write).
1515 #define MECR_PCMCIA(Nb) /* PCMCIA [0..1] */ \
1518 #define MECR_PCMCIA1 MECR_PCMCIA (1) /* PCMCIA 1 */
1520 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */
1522 ((((Tcpu) - 2)/2) << FShft (MECR_BSIO))
1524 ((((Tcpu) - 1)/2) << FShft (MECR_BSIO))
1525 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */
1528 ((((Tcpu) - 2)/2) << FShft (MECR_BSA))
1530 ((((Tcpu) - 1)/2) << FShft (MECR_BSA))
1531 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
1533 ((((Tcpu) - 2)/2) << FShft (MECR_BSM))
1535 ((((Tcpu) - 1)/2) << FShft (MECR_BSM))
1545 #define MDREFR_E0PIN (1 << 16)
1546 #define MDREFR_K0RUN (1 << 17)
1547 #define MDREFR_K0DB2 (1 << 18)
1548 #define MDREFR_E1PIN (1 << 20)
1549 #define MDREFR_K1RUN (1 << 21)
1550 #define MDREFR_K1DB2 (1 << 22)
1551 #define MDREFR_K2RUN (1 << 25)
1552 #define MDREFR_K2DB2 (1 << 26)
1553 #define MDREFR_EAPD (1 << 28)
1554 #define MDREFR_KAPD (1 << 29)
1555 #define MDREFR_SLFRSH (1 << 31)
1570 * (read/write).
1573 * SA-1100.]
1575 * (read/write).
1576 * [Bit LDD can be only read in versions 1.0 (rev. = 1)
1577 * and 1.1 (rev. = 2) of the StrongARM SA-1100, it can be
1578 * read and written (cleared) in versions 2.0 (rev. = 8)
1581 * (DMA) Base Address Register channel 1 (read/write).
1583 * (DMA) Current Address Register channel 1 (read).
1585 * (DMA) Base Address Register channel 2 (read/write).
1587 * (DMA) Current Address Register channel 2 (read).
1588 * LCCR1 Liquid Crystal Display (LCD) Control Register 1
1589 * (read/write).
1591 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1592 * StrongARM SA-1100, it can be written and read in
1595 * (read/write).
1597 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1598 * StrongARM SA-1100, it can be written and read in
1601 * (read/write).
1603 * versions 1.0 (rev. = 1) and 1.1 (rev. = 2) of the
1604 * StrongARM SA-1100, it can be written and read in
1607 * the StrongARM SA-1100.]
1618 #define LCD_4BitPSp /* LCD 4-Bit pixel Palette Space */ \
1621 #define LCD_8BitPSp /* LCD 8-Bit pixel Palette Space */ \
1624 #define LCD_12_16BitPSp /* LCD 12/16-Bit pixel */ \
1625 /* dummy-Palette Space [byte] */ \
1633 #define LCD_4Bit /* LCD 4-Bit pixel mode */ \
1635 #define LCD_8Bit /* LCD 8-Bit pixel mode */ \
1636 (1 << FShft (LCD_PBS))
1637 #define LCD_12_16Bit /* LCD 12/16-Bit pixel mode */ \
1641 #define LCD_Int11_1 0x1 /* LCD Intensity = 11.1% = 1/9 */
1642 #define LCD_Int20_0 0x2 /* LCD Intensity = 20.0% = 1/5 */
1647 #define LCD_Int50_0 0x7 /* LCD Intensity = 50.0% = 1/2 */
1654 #define LCD_Int100_0 0xE /* LCD Intensity = 100.0% = 1 */
1655 #define LCD_Int100_0A 0xF /* LCD Intensity = 100.0% = 1 */
1661 #define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
1665 #define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
1675 #define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
1678 #define LCCR0_BigEnd (LCCR0_BLE*1) /* Big Endian frame buffer */
1681 #define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome */
1683 #define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome */
1692 #define LCSR_BAU 0x00000002 /* Base Address Update (read) */
1695 #define LCSR_IOL 0x00000010 /* Input FIFO Over-run Lower */
1697 #define LCSR_IUL 0x00000020 /* Input FIFO Under-run Lower */
1699 #define LCSR_IOU 0x00000040 /* Input FIFO Over-run Upper */
1701 #define LCSR_IUU 0x00000080 /* Input FIFO Under-run Upper */
1703 #define LCSR_OOL 0x00000100 /* Output FIFO Over-run Lower */
1705 #define LCSR_OUL 0x00000200 /* Output FIFO Under-run Lower */
1707 #define LCSR_OOU 0x00000400 /* Output FIFO Over-run Upper */
1709 #define LCSR_OUU 0x00000800 /* Output FIFO Under-run Upper */
1712 #define LCCR1_PPL Fld (6, 4) /* Pixels Per Line/16 - 1 */
1714 (((Pixel) - 16)/16 << FShft (LCCR1_PPL))
1716 /* pulse Width - 1 [Tpix] (L_LCLK) */
1718 /* pulse Width [1..64 Tpix] */ \
1719 (((Tpix) - 1) << FShft (LCCR1_HSW))
1720 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
1721 /* count - 1 [Tpix] */
1722 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
1723 /* [1..256 Tpix] */ \
1724 (((Tpix) - 1) << FShft (LCCR1_ELW))
1725 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
1726 /* Wait count - 1 [Tpix] */
1727 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
1728 /* [1..256 Tpix] */ \
1729 (((Tpix) - 1) << FShft (LCCR1_BLW))
1731 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
1732 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
1733 (((Line) - 1) << FShft (LCCR2_LPP))
1735 /* Width - 1 [Tln] (L_FCLK) */
1737 /* Width [1..64 Tln] */ \
1738 (((Tln) - 1) << FShft (LCCR2_VSW))
1739 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
1741 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
1744 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
1746 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
1750 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor/2 - 2 */
1751 /* [1..255] (L_PCLK) */
1755 (((Div) - 4)/2 << FShft (LCCR3_PCD))
1759 (((Div) - 3)/2 << FShft (LCCR3_PCD))
1762 #define LCCR3_ACB Fld (8, 8) /* AC Bias clock half period - 1 */
1765 (((Div) - 2)/2 << FShft (LCCR3_ACB))
1769 (((Div) - 1)/2 << FShft (LCCR3_ACB))
1778 /* [1..15] */ \
1784 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
1790 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
1793 #define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
1794 #define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
1798 #define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */