Lines Matching refs:ldr
19 ldr r0, =PSSR
23 ldr ip, [r3]
59 ldr r2, [r1] @ Dummy read PXA3_MDCNFG
66 ldr r0, [r1, #PXA3_DDR_HCAL] @ Clear (and wait for) HCEN
69 1: ldr r0, [r1, #PXA3_DDR_HCAL]
73 ldr r0, [r1, #PXA3_RCOMP] @ Initiate RCOMP
80 ldr r0, [r1, #PXA3_DMCIER] @ set DMIER[EDLP]
84 ldr r0, [r1, #PXA3_DDR_HCAL] @ clear HCRNG, set HCPROG, HCEN
89 1: ldr r0, [r1, #PXA3_DMCISR]
93 ldr r0, [r1, #PXA3_MDCNFG] @ set PXA3_MDCNFG[DMCEN]
96 1: ldr r0, [r1, #PXA3_MDCNFG]
100 ldr r0, [r1, #PXA3_DDR_HCAL] @ set PXA3_DDR_HCAL[HCRNG]
104 ldr r0, [r1, #PXA3_DMCIER] @ Clear the interrupt