Lines Matching +full:0 +full:x9c
53 ? OMAP_CS3_PHYS : 0; in omap_cs0m_phys()
59 ? 0 : OMAP_CS3_PHYS; in omap_cs3_phys()
64 #define OMAP1_IO_OFFSET 0x00f00000 /* Virtual IO = 0xff0b0000 */
82 #define OMAP_MPU_TIMER1_BASE (0xfffec500)
83 #define OMAP_MPU_TIMER2_BASE (0xfffec600)
84 #define OMAP_MPU_TIMER3_BASE (0xfffec700)
88 #define MPU_TIMER_ST (1 << 0)
97 #define OMAP_MPU_WATCHDOG_BASE (0xfffec800)
98 #define OMAP_WDT_TIMER (OMAP_MPU_WATCHDOG_BASE + 0x0)
99 #define OMAP_WDT_LOAD_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
100 #define OMAP_WDT_READ_TIM (OMAP_MPU_WATCHDOG_BASE + 0x4)
101 #define OMAP_WDT_TIMER_MODE (OMAP_MPU_WATCHDOG_BASE + 0x8)
115 #define OMAP_IH1_BASE 0xfffecb00
116 #define OMAP_IH2_BASE 0xfffe0000
117 #define OMAP_IH2_0_BASE (0xfffe0000)
118 #define OMAP_IH2_1_BASE (0xfffe0100)
119 #define OMAP_IH2_2_BASE (0xfffe0200)
120 #define OMAP_IH2_3_BASE (0xfffe0300)
122 #define OMAP_IH1_ITR (OMAP_IH1_BASE + 0x00)
123 #define OMAP_IH1_MIR (OMAP_IH1_BASE + 0x04)
124 #define OMAP_IH1_SIR_IRQ (OMAP_IH1_BASE + 0x10)
125 #define OMAP_IH1_SIR_FIQ (OMAP_IH1_BASE + 0x14)
126 #define OMAP_IH1_CONTROL (OMAP_IH1_BASE + 0x18)
127 #define OMAP_IH1_ILR0 (OMAP_IH1_BASE + 0x1c)
128 #define OMAP_IH1_ISR (OMAP_IH1_BASE + 0x9c)
130 #define OMAP_IH2_ITR (OMAP_IH2_BASE + 0x00)
131 #define OMAP_IH2_MIR (OMAP_IH2_BASE + 0x04)
132 #define OMAP_IH2_SIR_IRQ (OMAP_IH2_BASE + 0x10)
133 #define OMAP_IH2_SIR_FIQ (OMAP_IH2_BASE + 0x14)
134 #define OMAP_IH2_CONTROL (OMAP_IH2_BASE + 0x18)
135 #define OMAP_IH2_ILR0 (OMAP_IH2_BASE + 0x1c)
136 #define OMAP_IH2_ISR (OMAP_IH2_BASE + 0x9c)
138 #define OMAP_IH2_0_ITR (OMAP_IH2_0_BASE + 0x00)
139 #define OMAP_IH2_0_MIR (OMAP_IH2_0_BASE + 0x04)
140 #define OMAP_IH2_0_SIR_IRQ (OMAP_IH2_0_BASE + 0x10)
141 #define OMAP_IH2_0_SIR_FIQ (OMAP_IH2_0_BASE + 0x14)
142 #define OMAP_IH2_0_CONTROL (OMAP_IH2_0_BASE + 0x18)
143 #define OMAP_IH2_0_ILR0 (OMAP_IH2_0_BASE + 0x1c)
144 #define OMAP_IH2_0_ISR (OMAP_IH2_0_BASE + 0x9c)
146 #define OMAP_IH2_1_ITR (OMAP_IH2_1_BASE + 0x00)
147 #define OMAP_IH2_1_MIR (OMAP_IH2_1_BASE + 0x04)
148 #define OMAP_IH2_1_SIR_IRQ (OMAP_IH2_1_BASE + 0x10)
149 #define OMAP_IH2_1_SIR_FIQ (OMAP_IH2_1_BASE + 0x14)
150 #define OMAP_IH2_1_CONTROL (OMAP_IH2_1_BASE + 0x18)
151 #define OMAP_IH2_1_ILR1 (OMAP_IH2_1_BASE + 0x1c)
152 #define OMAP_IH2_1_ISR (OMAP_IH2_1_BASE + 0x9c)
154 #define OMAP_IH2_2_ITR (OMAP_IH2_2_BASE + 0x00)
155 #define OMAP_IH2_2_MIR (OMAP_IH2_2_BASE + 0x04)
156 #define OMAP_IH2_2_SIR_IRQ (OMAP_IH2_2_BASE + 0x10)
157 #define OMAP_IH2_2_SIR_FIQ (OMAP_IH2_2_BASE + 0x14)
158 #define OMAP_IH2_2_CONTROL (OMAP_IH2_2_BASE + 0x18)
159 #define OMAP_IH2_2_ILR2 (OMAP_IH2_2_BASE + 0x1c)
160 #define OMAP_IH2_2_ISR (OMAP_IH2_2_BASE + 0x9c)
162 #define OMAP_IH2_3_ITR (OMAP_IH2_3_BASE + 0x00)
163 #define OMAP_IH2_3_MIR (OMAP_IH2_3_BASE + 0x04)
164 #define OMAP_IH2_3_SIR_IRQ (OMAP_IH2_3_BASE + 0x10)
165 #define OMAP_IH2_3_SIR_FIQ (OMAP_IH2_3_BASE + 0x14)
166 #define OMAP_IH2_3_CONTROL (OMAP_IH2_3_BASE + 0x18)
167 #define OMAP_IH2_3_ILR3 (OMAP_IH2_3_BASE + 0x1c)
168 #define OMAP_IH2_3_ISR (OMAP_IH2_3_BASE + 0x9c)
170 #define IRQ_ITR_REG_OFFSET 0x00
171 #define IRQ_MIR_REG_OFFSET 0x04
172 #define IRQ_SIR_IRQ_REG_OFFSET 0x10
173 #define IRQ_SIR_FIQ_REG_OFFSET 0x14
174 #define IRQ_CONTROL_REG_OFFSET 0x18
175 #define IRQ_ISR_REG_OFFSET 0x9c
176 #define IRQ_ILR0_REG_OFFSET 0x1c
177 #define IRQ_GMR_REG_OFFSET 0xa0
182 #define OMAP_TIMER32K_BASE 0xFFFBC400
189 #define TIPB_PUBLIC_CNTL_BASE 0xfffed300
190 #define MPU_PUBLIC_TIPB_CNTL (TIPB_PUBLIC_CNTL_BASE + 0x8)
191 #define TIPB_PRIVATE_CNTL_BASE 0xfffeca00
192 #define MPU_PRIVATE_TIPB_CNTL (TIPB_PRIVATE_CNTL_BASE + 0x8)
199 #define MPUI_BASE (0xfffec900)
200 #define MPUI_CTRL (MPUI_BASE + 0x0)
201 #define MPUI_DEBUG_ADDR (MPUI_BASE + 0x4)
202 #define MPUI_DEBUG_DATA (MPUI_BASE + 0x8)
203 #define MPUI_DEBUG_FLAG (MPUI_BASE + 0xc)
204 #define MPUI_STATUS_REG (MPUI_BASE + 0x10)
205 #define MPUI_DSP_STATUS (MPUI_BASE + 0x14)
206 #define MPUI_DSP_BOOT_CONFIG (MPUI_BASE + 0x18)
207 #define MPUI_DSP_API_CONFIG (MPUI_BASE + 0x1c)
214 #define OMAP_LPG1_BASE 0xfffbd000
215 #define OMAP_LPG2_BASE 0xfffbd800
216 #define OMAP_LPG1_LCR (OMAP_LPG1_BASE + 0x00)
217 #define OMAP_LPG1_PMR (OMAP_LPG1_BASE + 0x04)
218 #define OMAP_LPG2_LCR (OMAP_LPG2_BASE + 0x00)
219 #define OMAP_LPG2_PMR (OMAP_LPG2_BASE + 0x04)
227 #define OMAP1_DSP_BASE 0xE0000000
228 #define OMAP1_DSP_SIZE 0x28000
229 #define OMAP1_DSP_START 0xE0000000
231 #define OMAP1_DSPREG_BASE 0xE1000000
233 #define OMAP1_DSPREG_START 0xE1000000