Lines Matching +full:fast +full:- +full:mode
1 /* SPDX-License-Identifier: GPL-2.0 */
6 #include <asm/asm-offsets.h>
9 #include <asm/uaccess-asm.h>
13 @ -----------------
30 * (due to slow/fast restore user regs).
59 * ARMv7-M exception entry/exit macros.
65 * If exception is taken while in user mode, SP_main is
74 * When returning to kernel mode, we don't return from exception.
78 @ exception entry. Depending on the mode the cpu was in when the
86 @ we cannot rely on r0-r3 and r12 matching the value saved in the
87 @ exception frame because of tail-chaining. So these have to be
89 ldmia r12!, {r0-r3}
94 sub sp, #PT_REGS_SIZE-S_IP
95 stmdb sp!, {r0-r11}
98 @ r0-r7 are used for signals and never touched from now on. Clobbering
99 @ r8-r12 is OK.
101 ldmia r9!, {r8, r10-r12}
106 @ The cpu might automatically 8-byte align the stack. Bit 9
108 @ another 32-bit value is included in the stack.
116 @ store r13-r15, xPSR
117 stmia r8!, {r9-r12}
135 ldmia r12, {r1-r5}
137 @ an exception frame is always 8-byte aligned. To tell the hardware if
150 stmdb r2!, {r1, r3-r5}
151 ldmia sp, {r1, r3-r5}
153 stmdb r2!, {r0, r3-r5}
155 stmdb r2!, {r1, r3-r5}
161 @ restore original r4-r11
162 ldmia sp!, {r0-r11}
165 add sp, sp, #PT_REGS_SIZE-S_IP
174 @ mode. Useful in Thumb-2 mode where "stm/ldm rd, {sp, lr}^" is not
175 @ available. Should only be called from SVC mode
180 msr cpsr_c, \rtemp @ switch to the SYS mode
186 msr cpsr_c, \rtemp @ switch back to the SVC mode
192 msr cpsr_c, \rtemp @ switch to the SYS mode
198 msr cpsr_c, \rtemp @ switch back to the SVC mode
223 @ ARM mode SVC restore
226 @ We must avoid clrex due to Cortex-A15 erratum #830321
230 ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
232 @ Thumb mode SVC restore
236 @ We must avoid clrex due to Cortex-A15 erratum #830321
240 ldmia sp, {r0 - r12}
248 @ svc_exit_via_fiq - like svc_exit but switches to FIQ mode before exit
251 @ mode to restore the final part of the register state.
259 @ supplied rpsr. This is because the FIQ exceptions are not re-entrant
266 @ ARM mode restore
268 ldmib r0, {r1 - r14} @ abort is deadly from here onward (it will
277 @ Thumb mode restore
282 ldmia r0, {r2 - r12}
287 ldmia r0, {r0 - r1}
293 .macro restore_user_regs, fast = 0, offset = 0
310 @ ARM mode restore
318 @ We must avoid clrex due to Cortex-A15 erratum #830321
321 .if \fast
322 ldmdb r2, {r1 - lr}^ @ get calling r1 - lr
324 ldmdb r2, {r0 - lr}^ @ get calling r0 - lr
338 v7m_exception_slow_exit ret_r0 = \fast
340 @ Thumb mode restore
350 @ We must avoid clrex due to Cortex-A15 erratum #830321
353 .if \fast
354 ldmdb sp, {r1 - r12} @ get calling r1 - r12
356 ldmdb sp, {r0 - r12} @ get calling r0 - r12
358 add sp, sp, #PT_REGS_SIZE - S_SP
366 * between user and kernel mode.
371 stmdb sp!, {r0-r3, ip, lr}
373 ldmia sp!, {r0-r3, ip, lr}
383 stmdb sp!, {r0-r3, ip, lr}
385 ldmia sp!, {r0-r3, ip, lr}
401 ldmiacc r1, {r0 - r6} @ reload r0-r6
410 ldmiacc r1, {r0 - r6} @ reload r0-r6
419 * have in theory up to 7 arguments to a function - r0 to r6.
421 * r7 is reserved for the system call number for thumb mode.
452 str ip, [r0, #12] @ Stash IP on the mode stack