Lines Matching +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Device Tree Source for OMAP5 clock data
9 #clock-cells = <0>;
10 compatible = "fixed-clock";
11 clock-output-names = "pad_clks_src_ck";
12 clock-frequency = <12000000>;
16 #clock-cells = <0>;
17 compatible = "ti,gate-clock";
18 clock-output-names = "pad_clks_ck";
20 ti,bit-shift = <8>;
25 #clock-cells = <0>;
26 compatible = "fixed-clock";
27 clock-output-names = "secure_32k_clk_src_ck";
28 clock-frequency = <32768>;
32 #clock-cells = <0>;
33 compatible = "fixed-clock";
34 clock-output-names = "slimbus_src_clk";
35 clock-frequency = <12000000>;
39 #clock-cells = <0>;
40 compatible = "ti,gate-clock";
41 clock-output-names = "slimbus_clk";
43 ti,bit-shift = <10>;
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-output-names = "sys_32k_ck";
51 clock-frequency = <32768>;
55 #clock-cells = <0>;
56 compatible = "fixed-clock";
57 clock-output-names = "virt_12000000_ck";
58 clock-frequency = <12000000>;
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-output-names = "virt_13000000_ck";
65 clock-frequency = <13000000>;
69 #clock-cells = <0>;
70 compatible = "fixed-clock";
71 clock-output-names = "virt_16800000_ck";
72 clock-frequency = <16800000>;
76 #clock-cells = <0>;
77 compatible = "fixed-clock";
78 clock-output-names = "virt_19200000_ck";
79 clock-frequency = <19200000>;
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-output-names = "virt_26000000_ck";
86 clock-frequency = <26000000>;
90 #clock-cells = <0>;
91 compatible = "fixed-clock";
92 clock-output-names = "virt_27000000_ck";
93 clock-frequency = <27000000>;
97 #clock-cells = <0>;
98 compatible = "fixed-clock";
99 clock-output-names = "virt_38400000_ck";
100 clock-frequency = <38400000>;
104 #clock-cells = <0>;
105 compatible = "fixed-clock";
106 clock-output-names = "xclk60mhsp1_ck";
107 clock-frequency = <60000000>;
111 #clock-cells = <0>;
112 compatible = "fixed-clock";
113 clock-output-names = "xclk60mhsp2_ck";
114 clock-frequency = <60000000>;
118 #clock-cells = <0>;
119 compatible = "ti,omap4-dpll-m4xen-clock";
120 clock-output-names = "dpll_abe_ck";
126 #clock-cells = <0>;
127 compatible = "ti,omap4-dpll-x2-clock";
128 clock-output-names = "dpll_abe_x2_ck";
133 #clock-cells = <0>;
134 compatible = "ti,divider-clock";
135 clock-output-names = "dpll_abe_m2x2_ck";
137 ti,max-div = <31>;
139 ti,index-starts-at-one;
143 #clock-cells = <0>;
144 compatible = "fixed-factor-clock";
145 clock-output-names = "abe_24m_fclk";
147 clock-mult = <1>;
148 clock-div = <8>;
152 #clock-cells = <0>;
153 compatible = "ti,divider-clock";
154 clock-output-names = "abe_clk";
156 ti,max-div = <4>;
158 ti,index-power-of-two;
162 #clock-cells = <0>;
163 compatible = "ti,divider-clock";
164 clock-output-names = "abe_iclk";
166 ti,bit-shift = <24>;
172 #clock-cells = <0>;
173 compatible = "fixed-factor-clock";
174 clock-output-names = "abe_lp_clk_div";
176 clock-mult = <1>;
177 clock-div = <16>;
181 #clock-cells = <0>;
182 compatible = "ti,divider-clock";
183 clock-output-names = "dpll_abe_m3x2_ck";
185 ti,max-div = <31>;
187 ti,index-starts-at-one;
191 #clock-cells = <0>;
192 compatible = "ti,mux-clock";
193 clock-output-names = "dpll_core_byp_mux";
195 ti,bit-shift = <23>;
200 #clock-cells = <0>;
201 compatible = "ti,omap4-dpll-core-clock";
202 clock-output-names = "dpll_core_ck";
208 #clock-cells = <0>;
209 compatible = "ti,omap4-dpll-x2-clock";
210 clock-output-names = "dpll_core_x2_ck";
215 #clock-cells = <0>;
216 compatible = "ti,divider-clock";
217 clock-output-names = "dpll_core_h21x2_ck";
219 ti,max-div = <63>;
221 ti,index-starts-at-one;
225 #clock-cells = <0>;
226 compatible = "fixed-factor-clock";
227 clock-output-names = "c2c_fclk";
229 clock-mult = <1>;
230 clock-div = <1>;
234 #clock-cells = <0>;
235 compatible = "fixed-factor-clock";
236 clock-output-names = "c2c_iclk";
238 clock-mult = <1>;
239 clock-div = <2>;
243 #clock-cells = <0>;
244 compatible = "ti,divider-clock";
245 clock-output-names = "dpll_core_h11x2_ck";
247 ti,max-div = <63>;
249 ti,index-starts-at-one;
253 #clock-cells = <0>;
254 compatible = "ti,divider-clock";
255 clock-output-names = "dpll_core_h12x2_ck";
257 ti,max-div = <63>;
259 ti,index-starts-at-one;
263 #clock-cells = <0>;
264 compatible = "ti,divider-clock";
265 clock-output-names = "dpll_core_h13x2_ck";
267 ti,max-div = <63>;
269 ti,index-starts-at-one;
273 #clock-cells = <0>;
274 compatible = "ti,divider-clock";
275 clock-output-names = "dpll_core_h14x2_ck";
277 ti,max-div = <63>;
279 ti,index-starts-at-one;
283 #clock-cells = <0>;
284 compatible = "ti,divider-clock";
285 clock-output-names = "dpll_core_h22x2_ck";
287 ti,max-div = <63>;
289 ti,index-starts-at-one;
293 #clock-cells = <0>;
294 compatible = "ti,divider-clock";
295 clock-output-names = "dpll_core_h23x2_ck";
297 ti,max-div = <63>;
299 ti,index-starts-at-one;
303 #clock-cells = <0>;
304 compatible = "ti,divider-clock";
305 clock-output-names = "dpll_core_h24x2_ck";
307 ti,max-div = <63>;
309 ti,index-starts-at-one;
313 #clock-cells = <0>;
314 compatible = "ti,divider-clock";
315 clock-output-names = "dpll_core_m2_ck";
317 ti,max-div = <31>;
319 ti,index-starts-at-one;
323 #clock-cells = <0>;
324 compatible = "ti,divider-clock";
325 clock-output-names = "dpll_core_m3x2_ck";
327 ti,max-div = <31>;
329 ti,index-starts-at-one;
333 #clock-cells = <0>;
334 compatible = "fixed-factor-clock";
335 clock-output-names = "iva_dpll_hs_clk_div";
337 clock-mult = <1>;
338 clock-div = <1>;
342 #clock-cells = <0>;
343 compatible = "ti,mux-clock";
344 clock-output-names = "dpll_iva_byp_mux";
346 ti,bit-shift = <23>;
351 #clock-cells = <0>;
352 compatible = "ti,omap4-dpll-clock";
353 clock-output-names = "dpll_iva_ck";
356 assigned-clocks = <&dpll_iva_ck>;
357 assigned-clock-rates = <1165000000>;
361 #clock-cells = <0>;
362 compatible = "ti,omap4-dpll-x2-clock";
363 clock-output-names = "dpll_iva_x2_ck";
368 #clock-cells = <0>;
369 compatible = "ti,divider-clock";
370 clock-output-names = "dpll_iva_h11x2_ck";
372 ti,max-div = <63>;
374 ti,index-starts-at-one;
375 assigned-clocks = <&dpll_iva_h11x2_ck>;
376 assigned-clock-rates = <465920000>;
380 #clock-cells = <0>;
381 compatible = "ti,divider-clock";
382 clock-output-names = "dpll_iva_h12x2_ck";
384 ti,max-div = <63>;
386 ti,index-starts-at-one;
387 assigned-clocks = <&dpll_iva_h12x2_ck>;
388 assigned-clock-rates = <388300000>;
392 #clock-cells = <0>;
393 compatible = "fixed-factor-clock";
394 clock-output-names = "mpu_dpll_hs_clk_div";
396 clock-mult = <1>;
397 clock-div = <1>;
401 #clock-cells = <0>;
402 compatible = "ti,omap5-mpu-dpll-clock";
403 clock-output-names = "dpll_mpu_ck";
409 #clock-cells = <0>;
410 compatible = "ti,divider-clock";
411 clock-output-names = "dpll_mpu_m2_ck";
413 ti,max-div = <31>;
415 ti,index-starts-at-one;
419 #clock-cells = <0>;
420 compatible = "fixed-factor-clock";
421 clock-output-names = "per_dpll_hs_clk_div";
423 clock-mult = <1>;
424 clock-div = <2>;
428 #clock-cells = <0>;
429 compatible = "fixed-factor-clock";
430 clock-output-names = "usb_dpll_hs_clk_div";
432 clock-mult = <1>;
433 clock-div = <3>;
437 #clock-cells = <0>;
438 compatible = "ti,divider-clock";
439 clock-output-names = "l3_iclk_div";
440 ti,max-div = <2>;
441 ti,bit-shift = <4>;
444 ti,index-power-of-two;
448 #clock-cells = <0>;
449 compatible = "fixed-factor-clock";
450 clock-output-names = "gpu_l3_iclk";
452 clock-mult = <1>;
453 clock-div = <1>;
457 #clock-cells = <0>;
458 compatible = "ti,divider-clock";
459 clock-output-names = "l4_root_clk_div";
460 ti,max-div = <2>;
461 ti,bit-shift = <8>;
464 ti,index-power-of-two;
468 #clock-cells = <0>;
469 compatible = "ti,gate-clock";
470 clock-output-names = "slimbus1_slimbus_clk";
472 ti,bit-shift = <11>;
477 #clock-cells = <0>;
478 compatible = "ti,divider-clock";
479 clock-output-names = "aess_fclk";
481 ti,bit-shift = <24>;
482 ti,max-div = <2>;
487 #clock-cells = <0>;
488 compatible = "ti,mux-clock";
489 clock-output-names = "mcasp_sync_mux_ck";
491 ti,bit-shift = <26>;
496 #clock-cells = <0>;
497 compatible = "ti,mux-clock";
498 clock-output-names = "mcasp_gfclk";
500 ti,bit-shift = <24>;
505 #clock-cells = <0>;
506 compatible = "fixed-clock";
507 clock-output-names = "dummy_ck";
508 clock-frequency = <0>;
513 #clock-cells = <0>;
514 compatible = "ti,mux-clock";
515 clock-output-names = "sys_clkin";
518 ti,index-starts-at-one;
522 #clock-cells = <0>;
523 compatible = "ti,mux-clock";
524 clock-output-names = "abe_dpll_bypass_clk_mux";
530 #clock-cells = <0>;
531 compatible = "ti,mux-clock";
532 clock-output-names = "abe_dpll_clk_mux";
538 #clock-cells = <0>;
539 compatible = "fixed-factor-clock";
540 clock-output-names = "custefuse_sys_gfclk_div";
542 clock-mult = <1>;
543 clock-div = <2>;
547 #clock-cells = <0>;
548 compatible = "fixed-factor-clock";
549 clock-output-names = "dss_syc_gfclk_div";
551 clock-mult = <1>;
552 clock-div = <1>;
556 #clock-cells = <0>;
557 compatible = "ti,mux-clock";
558 clock-output-names = "wkupaon_iclk_mux";
564 #clock-cells = <0>;
565 compatible = "fixed-factor-clock";
566 clock-output-names = "l3instr_ts_gclk_div";
568 clock-mult = <1>;
569 clock-div = <1>;
576 #clock-cells = <0>;
577 compatible = "ti,mux-clock";
578 clock-output-names = "dpll_per_byp_mux";
580 ti,bit-shift = <23>;
585 #clock-cells = <0>;
586 compatible = "ti,omap4-dpll-clock";
587 clock-output-names = "dpll_per_ck";
593 #clock-cells = <0>;
594 compatible = "ti,omap4-dpll-x2-clock";
595 clock-output-names = "dpll_per_x2_ck";
600 #clock-cells = <0>;
601 compatible = "ti,divider-clock";
602 clock-output-names = "dpll_per_h11x2_ck";
604 ti,max-div = <63>;
606 ti,index-starts-at-one;
610 #clock-cells = <0>;
611 compatible = "ti,divider-clock";
612 clock-output-names = "dpll_per_h12x2_ck";
614 ti,max-div = <63>;
616 ti,index-starts-at-one;
620 #clock-cells = <0>;
621 compatible = "ti,divider-clock";
622 clock-output-names = "dpll_per_h14x2_ck";
624 ti,max-div = <63>;
626 ti,index-starts-at-one;
630 #clock-cells = <0>;
631 compatible = "ti,divider-clock";
632 clock-output-names = "dpll_per_m2_ck";
634 ti,max-div = <31>;
636 ti,index-starts-at-one;
640 #clock-cells = <0>;
641 compatible = "ti,divider-clock";
642 clock-output-names = "dpll_per_m2x2_ck";
644 ti,max-div = <31>;
646 ti,index-starts-at-one;
650 #clock-cells = <0>;
651 compatible = "ti,divider-clock";
652 clock-output-names = "dpll_per_m3x2_ck";
654 ti,max-div = <31>;
656 ti,index-starts-at-one;
660 #clock-cells = <0>;
661 compatible = "ti,omap4-dpll-clock";
662 clock-output-names = "dpll_unipro1_ck";
668 #clock-cells = <0>;
669 compatible = "fixed-factor-clock";
670 clock-output-names = "dpll_unipro1_clkdcoldo";
672 clock-mult = <1>;
673 clock-div = <1>;
677 #clock-cells = <0>;
678 compatible = "ti,divider-clock";
679 clock-output-names = "dpll_unipro1_m2_ck";
681 ti,max-div = <127>;
683 ti,index-starts-at-one;
687 #clock-cells = <0>;
688 compatible = "ti,omap4-dpll-clock";
689 clock-output-names = "dpll_unipro2_ck";
695 #clock-cells = <0>;
696 compatible = "fixed-factor-clock";
697 clock-output-names = "dpll_unipro2_clkdcoldo";
699 clock-mult = <1>;
700 clock-div = <1>;
704 #clock-cells = <0>;
705 compatible = "ti,divider-clock";
706 clock-output-names = "dpll_unipro2_m2_ck";
708 ti,max-div = <127>;
710 ti,index-starts-at-one;
714 #clock-cells = <0>;
715 compatible = "ti,mux-clock";
716 clock-output-names = "dpll_usb_byp_mux";
718 ti,bit-shift = <23>;
723 #clock-cells = <0>;
724 compatible = "ti,omap4-dpll-j-type-clock";
725 clock-output-names = "dpll_usb_ck";
731 #clock-cells = <0>;
732 compatible = "fixed-factor-clock";
733 clock-output-names = "dpll_usb_clkdcoldo";
735 clock-mult = <1>;
736 clock-div = <1>;
740 #clock-cells = <0>;
741 compatible = "ti,divider-clock";
742 clock-output-names = "dpll_usb_m2_ck";
744 ti,max-div = <127>;
746 ti,index-starts-at-one;
750 #clock-cells = <0>;
751 compatible = "fixed-factor-clock";
752 clock-output-names = "func_128m_clk";
754 clock-mult = <1>;
755 clock-div = <2>;
759 #clock-cells = <0>;
760 compatible = "fixed-factor-clock";
761 clock-output-names = "func_12m_fclk";
763 clock-mult = <1>;
764 clock-div = <16>;
768 #clock-cells = <0>;
769 compatible = "fixed-factor-clock";
770 clock-output-names = "func_24m_clk";
772 clock-mult = <1>;
773 clock-div = <4>;
777 #clock-cells = <0>;
778 compatible = "fixed-factor-clock";
779 clock-output-names = "func_48m_fclk";
781 clock-mult = <1>;
782 clock-div = <4>;
786 #clock-cells = <0>;
787 compatible = "fixed-factor-clock";
788 clock-output-names = "func_96m_fclk";
790 clock-mult = <1>;
791 clock-div = <2>;
795 #clock-cells = <0>;
796 compatible = "ti,divider-clock";
797 clock-output-names = "l3init_60m_fclk";
804 #clock-cells = <0>;
805 compatible = "ti,gate-clock";
806 clock-output-names = "iss_ctrlclk";
808 ti,bit-shift = <8>;
813 #clock-cells = <0>;
814 compatible = "ti,gate-clock";
815 clock-output-names = "lli_txphy_clk";
817 ti,bit-shift = <8>;
822 #clock-cells = <0>;
823 compatible = "ti,gate-clock";
824 clock-output-names = "lli_txphy_ls_clk";
826 ti,bit-shift = <9>;
831 #clock-cells = <0>;
832 compatible = "ti,gate-clock";
833 clock-output-names = "usb_phy_cm_clk32k";
835 ti,bit-shift = <8>;
840 #clock-cells = <0>;
841 compatible = "ti,divider-clock";
842 clock-output-names = "fdif_fclk";
844 ti,bit-shift = <24>;
845 ti,max-div = <2>;
850 #clock-cells = <0>;
851 compatible = "ti,mux-clock";
852 clock-output-names = "gpu_core_gclk_mux";
854 ti,bit-shift = <24>;
859 #clock-cells = <0>;
860 compatible = "ti,mux-clock";
861 clock-output-names = "gpu_hyd_gclk_mux";
863 ti,bit-shift = <25>;
868 #clock-cells = <0>;
869 compatible = "ti,divider-clock";
870 clock-output-names = "hsi_fclk";
872 ti,bit-shift = <24>;
873 ti,max-div = <2>;
881 clock-output-names = "l3init_clkdm";
888 #clock-cells = <0>;
889 compatible = "ti,composite-no-wait-gate-clock";
890 clock-output-names = "auxclk0_src_gate_ck";
892 ti,bit-shift = <8>;
897 #clock-cells = <0>;
898 compatible = "ti,composite-mux-clock";
899 clock-output-names = "auxclk0_src_mux_ck";
901 ti,bit-shift = <1>;
906 #clock-cells = <0>;
907 compatible = "ti,composite-clock";
908 clock-output-names = "auxclk0_src_ck";
913 #clock-cells = <0>;
914 compatible = "ti,divider-clock";
915 clock-output-names = "auxclk0_ck";
917 ti,bit-shift = <16>;
918 ti,max-div = <16>;
923 #clock-cells = <0>;
924 compatible = "ti,composite-no-wait-gate-clock";
925 clock-output-names = "auxclk1_src_gate_ck";
927 ti,bit-shift = <8>;
932 #clock-cells = <0>;
933 compatible = "ti,composite-mux-clock";
934 clock-output-names = "auxclk1_src_mux_ck";
936 ti,bit-shift = <1>;
941 #clock-cells = <0>;
942 compatible = "ti,composite-clock";
943 clock-output-names = "auxclk1_src_ck";
948 #clock-cells = <0>;
949 compatible = "ti,divider-clock";
950 clock-output-names = "auxclk1_ck";
952 ti,bit-shift = <16>;
953 ti,max-div = <16>;
958 #clock-cells = <0>;
959 compatible = "ti,composite-no-wait-gate-clock";
960 clock-output-names = "auxclk2_src_gate_ck";
962 ti,bit-shift = <8>;
967 #clock-cells = <0>;
968 compatible = "ti,composite-mux-clock";
969 clock-output-names = "auxclk2_src_mux_ck";
971 ti,bit-shift = <1>;
976 #clock-cells = <0>;
977 compatible = "ti,composite-clock";
978 clock-output-names = "auxclk2_src_ck";
983 #clock-cells = <0>;
984 compatible = "ti,divider-clock";
985 clock-output-names = "auxclk2_ck";
987 ti,bit-shift = <16>;
988 ti,max-div = <16>;
993 #clock-cells = <0>;
994 compatible = "ti,composite-no-wait-gate-clock";
995 clock-output-names = "auxclk3_src_gate_ck";
997 ti,bit-shift = <8>;
1002 #clock-cells = <0>;
1003 compatible = "ti,composite-mux-clock";
1004 clock-output-names = "auxclk3_src_mux_ck";
1006 ti,bit-shift = <1>;
1011 #clock-cells = <0>;
1012 compatible = "ti,composite-clock";
1013 clock-output-names = "auxclk3_src_ck";
1018 #clock-cells = <0>;
1019 compatible = "ti,divider-clock";
1020 clock-output-names = "auxclk3_ck";
1022 ti,bit-shift = <16>;
1023 ti,max-div = <16>;
1028 #clock-cells = <0>;
1029 compatible = "ti,composite-no-wait-gate-clock";
1030 clock-output-names = "auxclk4_src_gate_ck";
1032 ti,bit-shift = <8>;
1037 #clock-cells = <0>;
1038 compatible = "ti,composite-mux-clock";
1039 clock-output-names = "auxclk4_src_mux_ck";
1041 ti,bit-shift = <1>;
1046 #clock-cells = <0>;
1047 compatible = "ti,composite-clock";
1048 clock-output-names = "auxclk4_src_ck";
1053 #clock-cells = <0>;
1054 compatible = "ti,divider-clock";
1055 clock-output-names = "auxclk4_ck";
1057 ti,bit-shift = <16>;
1058 ti,max-div = <16>;
1063 #clock-cells = <0>;
1064 compatible = "ti,mux-clock";
1065 clock-output-names = "auxclkreq0_ck";
1067 ti,bit-shift = <2>;
1072 #clock-cells = <0>;
1073 compatible = "ti,mux-clock";
1074 clock-output-names = "auxclkreq1_ck";
1076 ti,bit-shift = <2>;
1081 #clock-cells = <0>;
1082 compatible = "ti,mux-clock";
1083 clock-output-names = "auxclkreq2_ck";
1085 ti,bit-shift = <2>;
1090 #clock-cells = <0>;
1091 compatible = "ti,mux-clock";
1092 clock-output-names = "auxclkreq3_ck";
1094 ti,bit-shift = <2>;
1101 compatible = "ti,omap4-cm";
1102 clock-output-names = "mpu_cm";
1104 #address-cells = <1>;
1105 #size-cells = <1>;
1110 clock-output-names = "mpu_clkctrl";
1112 #clock-cells = <2>;
1117 compatible = "ti,omap4-cm";
1118 clock-output-names = "dsp_cm";
1120 #address-cells = <1>;
1121 #size-cells = <1>;
1126 clock-output-names = "dsp_clkctrl";
1128 #clock-cells = <2>;
1133 compatible = "ti,omap4-cm";
1134 clock-output-names = "abe_cm";
1136 #address-cells = <1>;
1137 #size-cells = <1>;
1142 clock-output-names = "abe_clkctrl";
1144 #clock-cells = <2>;
1152 compatible = "ti,omap4-cm";
1153 clock-output-names = "l3main1_cm";
1155 #address-cells = <1>;
1156 #size-cells = <1>;
1161 clock-output-names = "l3main1_clkctrl";
1163 #clock-cells = <2>;
1168 compatible = "ti,omap4-cm";
1169 clock-output-names = "l3main2_cm";
1171 #address-cells = <1>;
1172 #size-cells = <1>;
1177 clock-output-names = "l3main2_clkctrl";
1179 #clock-cells = <2>;
1184 compatible = "ti,omap4-cm";
1185 clock-output-names = "ipu_cm";
1187 #address-cells = <1>;
1188 #size-cells = <1>;
1193 clock-output-names = "ipu_clkctrl";
1195 #clock-cells = <2>;
1200 compatible = "ti,omap4-cm";
1201 clock-output-names = "dma_cm";
1203 #address-cells = <1>;
1204 #size-cells = <1>;
1209 clock-output-names = "dma_clkctrl";
1211 #clock-cells = <2>;
1216 compatible = "ti,omap4-cm";
1217 clock-output-names = "emif_cm";
1219 #address-cells = <1>;
1220 #size-cells = <1>;
1225 clock-output-names = "emif_clkctrl";
1227 #clock-cells = <2>;
1232 compatible = "ti,omap4-cm";
1233 clock-output-names = "l4cfg_cm";
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1241 clock-output-names = "l4cfg_clkctrl";
1243 #clock-cells = <2>;
1248 compatible = "ti,omap4-cm";
1249 clock-output-names = "l3instr_cm";
1251 #address-cells = <1>;
1252 #size-cells = <1>;
1257 clock-output-names = "l3instr_clkctrl";
1259 #clock-cells = <2>;
1263 l4per_cm: clock@1000 {
1264 compatible = "ti,omap4-cm";
1265 clock-output-names = "l4per_cm";
1267 #address-cells = <1>;
1268 #size-cells = <1>;
1271 l4per_clkctrl: clock@20 {
1273 clock-output-names = "l4per_clkctrl";
1275 #clock-cells = <2>;
1278 l4sec_clkctrl: clock@1a0 {
1280 clock-output-names = "l4sec_clkctrl";
1282 #clock-cells = <2>;
1287 compatible = "ti,omap4-cm";
1288 clock-output-names = "dss_cm";
1290 #address-cells = <1>;
1291 #size-cells = <1>;
1296 clock-output-names = "dss_clkctrl";
1298 #clock-cells = <2>;
1303 compatible = "ti,omap4-cm";
1304 clock-output-names = "gpu_cm";
1306 #address-cells = <1>;
1307 #size-cells = <1>;
1312 clock-output-names = "gpu_clkctrl";
1314 #clock-cells = <2>;
1319 compatible = "ti,omap4-cm";
1320 clock-output-names = "l3init_cm";
1322 #address-cells = <1>;
1323 #size-cells = <1>;
1328 clock-output-names = "l3init_clkctrl";
1330 #clock-cells = <2>;
1337 compatible = "ti,omap4-cm";
1338 clock-output-names = "wkupaon_cm";
1340 #address-cells = <1>;
1341 #size-cells = <1>;
1346 clock-output-names = "wkupaon_clkctrl";
1348 #clock-cells = <2>;
1355 #clock-cells = <0>;
1356 compatible = "ti,gate-clock";
1357 clock-output-names = "fref_xtal_ck";
1359 ti,bit-shift = <28>;