Lines Matching +full:0 +full:x1b00
47 #size-cells = <0>;
48 cpu@0 {
52 reg = <0>;
87 opp-supported-hw = <0x06 0x0010>;
95 opp-supported-hw = <0x01 0x00FF>;
103 opp-supported-hw = <0x06 0x0020>;
111 opp-supported-hw = <0x01 0xFFFF>;
118 opp-supported-hw = <0x06 0x0040>;
125 opp-supported-hw = <0x01 0xFFFF>;
132 opp-supported-hw = <0x06 0x0080>;
139 opp-supported-hw = <0x01 0xFFFF>;
146 opp-supported-hw = <0x06 0x0100>;
153 opp-supported-hw = <0x04 0x0200>;
159 clocks = <&l3_clkctrl AM3_L3_L3_INSTR_CLKCTRL 0>;
164 ranges = <0x0 0x4b000000 0x1000000>;
168 clocks = <&l3_aon_clkctrl AM3_L3_AON_DEBUGSS_CLKCTRL 0>;
172 ranges = <0x0 0x140000 0xec0000>;
174 pmu@0 {
199 clocks = <&l3_clkctrl AM3_L3_L3_MAIN_CLKCTRL 0>;
220 reg = <0x48200000 0x1000>;
225 reg = <0x49000000 0x4>;
227 clocks = <&l3_clkctrl AM3_L3_TPCC_CLKCTRL 0>;
231 ranges = <0x0 0x49000000 0x10000>;
233 edma: dma@0 {
235 reg = <0 0x10000>;
244 <&edma_tptc2 0>;
252 reg = <0x49800000 0x4>,
253 <0x49800010 0x4>;
259 clocks = <&l3_clkctrl AM3_L3_TPTC0_CLKCTRL 0>;
263 ranges = <0x0 0x49800000 0x100000>;
265 edma_tptc0: dma@0 {
267 reg = <0 0x100000>;
275 reg = <0x49900000 0x4>,
276 <0x49900010 0x4>;
282 clocks = <&l3_clkctrl AM3_L3_TPTC1_CLKCTRL 0>;
286 ranges = <0x0 0x49900000 0x100000>;
288 edma_tptc1: dma@0 {
290 reg = <0 0x100000>;
298 reg = <0x49a00000 0x4>,
299 <0x49a00010 0x4>;
305 clocks = <&l3_clkctrl AM3_L3_TPTC2_CLKCTRL 0>;
309 ranges = <0x0 0x49a00000 0x100000>;
311 edma_tptc2: dma@0 {
313 reg = <0 0x100000>;
321 reg = <0x478102fc 0x4>,
322 <0x47810110 0x4>,
323 <0x47810114 0x4>;
333 clocks = <&l3s_clkctrl AM3_L3S_MMC3_CLKCTRL 0>;
337 ranges = <0x0 0x47810000 0x1000>;
339 mmc3: mmc@0 {
343 reg = <0x0 0x1000>;
350 reg = <0x47400000 0x4>,
351 <0x47400010 0x4>;
362 clocks = <&l3s_clkctrl AM3_L3S_USB_OTG_HS_CLKCTRL 0>;
366 ranges = <0x0 0x47400000 0x8000>;
370 reg = <0x1300 0x100>;
373 #phy-cells = <0>;
378 reg = <0x1400 0x400>,
379 <0x1000 0x200>;
391 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
392 &cppi41dma 2 0 &cppi41dma 3 0
393 &cppi41dma 4 0 &cppi41dma 5 0
394 &cppi41dma 6 0 &cppi41dma 7 0
395 &cppi41dma 8 0 &cppi41dma 9 0
396 &cppi41dma 10 0 &cppi41dma 11 0
397 &cppi41dma 12 0 &cppi41dma 13 0
398 &cppi41dma 14 0 &cppi41dma 0 1
417 reg = <0x1b00 0x100>;
420 #phy-cells = <0>;
425 reg = <0x1c00 0x400>,
426 <0x1800 0x200>;
437 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
438 &cppi41dma 17 0 &cppi41dma 18 0
439 &cppi41dma 19 0 &cppi41dma 20 0
440 &cppi41dma 21 0 &cppi41dma 22 0
441 &cppi41dma 23 0 &cppi41dma 24 0
442 &cppi41dma 25 0 &cppi41dma 26 0
443 &cppi41dma 27 0 &cppi41dma 28 0
444 &cppi41dma 29 0 &cppi41dma 15 1
463 reg = <0x0000 0x1000>,
464 <0x2000 0x1000>,
465 <0x3000 0x1000>,
466 <0x4000 0x4000>;
481 clocks = <&l3_clkctrl AM3_L3_OCMCRAM_CLKCTRL 0>;
486 ranges = <0 0x40300000 0x10000>;
488 ocmcram: sram@0 {
490 reg = <0 0x10000>; /* 64k */
491 ranges = <0 0 0x10000>;
495 pm_sram_code: pm-code-sram@0 {
497 reg = <0x0 0x1000>;
503 reg = <0x1000 0x1000>;
511 reg = <0x4c000000 0x4>;
513 clocks = <&l3_clkctrl AM3_L3_EMIF_CLKCTRL 0>;
518 ranges = <0x0 0x4c000000 0x1000000>;
520 emif: emif@0 {
522 reg = <0 0x1000000>;
531 reg = <0x50000000 4>,
532 <0x50000010 4>,
533 <0x50000014 4>;
539 clocks = <&l3s_clkctrl AM3_L3S_GPMC_CLKCTRL 0>;
543 ranges = <0x50000000 0x50000000 0x00001000>, /* regs */
544 <0x00000000 0x00000000 0x40000000>; /* data */
548 reg = <0x50000000 0x2000>;
550 dmas = <&edma 52 0>;
566 reg = <0x53100100 0x4>,
567 <0x53100110 0x4>,
568 <0x53100114 0x4>;
577 clocks = <&l3_clkctrl AM3_L3_SHAM_CLKCTRL 0>;
581 ranges = <0x0 0x53100000 0x1000>;
583 sham: sham@0 {
585 reg = <0 0x200>;
587 dmas = <&edma 36 0>;
594 reg = <0x53500080 0x4>,
595 <0x53500084 0x4>,
596 <0x53500088 0x4>;
606 clocks = <&l3_clkctrl AM3_L3_AES_CLKCTRL 0>;
610 ranges = <0x0 0x53500000 0x1000>;
612 aes: aes@0 {
614 reg = <0 0xa0>;
616 dmas = <&edma 6 0>,
617 <&edma 5 0>;
624 reg = <0x5600fe00 0x4>,
625 <0x5600fe10 0x4>;
633 clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
636 resets = <&prm_gfx 0>;
640 ranges = <0 0x56000000 0x1000000>;
656 reg = <0xc00 0x100>;
658 #power-domain-cells = <0>;
663 reg = <0xd00 0x100>;
665 #power-domain-cells = <0>;
670 reg = <0xe00 0x100>;
671 #power-domain-cells = <0>;
676 reg = <0xf00 0x100>;
682 reg = <0x1000 0x100>;
683 #power-domain-cells = <0>;
688 reg = <0x1100 0x100>;
689 #power-domain-cells = <0>;
695 reg = <0x1200 0x100>;
696 #power-domain-cells = <0>;
702 clocks = <&l4_wkup_clkctrl AM3_L4_WKUP_TIMER1_CLKCTRL 0>,
703 <&l4_wkup_clkctrl AM3_L4_WKUP_L4_WKUP_CLKCTRL 0>;
707 timer@0 {
715 clocks = <&l4ls_clkctrl AM3_L4LS_TIMER2_CLKCTRL 0>,
716 <&l4ls_clkctrl AM3_L4LS_L4_LS_CLKCTRL 0>;
720 timer@0 {