Lines Matching +full:pwm +full:- +full:names
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
4 * This file is dual-licensed: you can use it either under the terms
43 #include "../armv7-m.dtsi"
44 #include <dt-bindings/clock/stm32fx-clock.h>
45 #include <dt-bindings/mfd/stm32f7-rcc.h>
48 #address-cells = <1>;
49 #size-cells = <1>;
52 clk_hse: clk-hse {
53 #clock-cells = <0>;
54 compatible = "fixed-clock";
55 clock-frequency = <0>;
58 clk-lse {
59 #clock-cells = <0>;
60 compatible = "fixed-clock";
61 clock-frequency = <32768>;
64 clk-lsi {
65 #clock-cells = <0>;
66 compatible = "fixed-clock";
67 clock-frequency = <32000>;
70 clk_i2s_ckin: clk-i2s-ckin {
71 #clock-cells = <0>;
72 compatible = "fixed-clock";
73 clock-frequency = <48000000>;
79 #address-cells = <1>;
80 #size-cells = <0>;
81 compatible = "st,stm32-timers";
84 clock-names = "int";
87 pwm {
88 compatible = "st,stm32-pwm";
89 #pwm-cells = <3>;
94 compatible = "st,stm32-timer-trigger";
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "st,stm32-timers";
106 clock-names = "int";
109 pwm {
110 compatible = "st,stm32-pwm";
111 #pwm-cells = <3>;
116 compatible = "st,stm32-timer-trigger";
123 #address-cells = <1>;
124 #size-cells = <0>;
125 compatible = "st,stm32-timers";
128 clock-names = "int";
131 pwm {
132 compatible = "st,stm32-pwm";
133 #pwm-cells = <3>;
138 compatible = "st,stm32-timer-trigger";
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "st,stm32-timers";
150 clock-names = "int";
153 pwm {
154 compatible = "st,stm32-pwm";
155 #pwm-cells = <3>;
160 compatible = "st,stm32-timer-trigger";
167 #address-cells = <1>;
168 #size-cells = <0>;
169 compatible = "st,stm32-timers";
172 clock-names = "int";
176 compatible = "st,stm32-timer-trigger";
183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "st,stm32-timers";
188 clock-names = "int";
192 compatible = "st,stm32-timer-trigger";
199 #address-cells = <1>;
200 #size-cells = <0>;
201 compatible = "st,stm32-timers";
204 clock-names = "int";
207 pwm {
208 compatible = "st,stm32-pwm";
209 #pwm-cells = <3>;
214 compatible = "st,stm32-timer-trigger";
221 compatible = "st,stm32-timers";
224 clock-names = "int";
227 pwm {
228 compatible = "st,stm32-pwm";
229 #pwm-cells = <3>;
235 compatible = "st,stm32-timers";
238 clock-names = "int";
241 pwm {
242 compatible = "st,stm32-pwm";
243 #pwm-cells = <3>;
249 compatible = "st,stm32-rtc";
252 assigned-clocks = <&rcc 1 CLK_RTC>;
253 assigned-clock-parents = <&rcc 1 CLK_LSE>;
254 interrupt-parent = <&exti>;
261 compatible = "st,stm32f4-bxcan";
264 interrupt-names = "tx", "rx0", "rx1", "sce";
272 compatible = "st,stm32f4-gcan", "syscon";
278 compatible = "st,stm32f7-uart";
286 compatible = "st,stm32f7-uart";
294 compatible = "st,stm32f7-uart";
302 compatible = "st,stm32f7-uart";
310 compatible = "st,stm32f7-i2c";
316 #address-cells = <1>;
317 #size-cells = <0>;
322 compatible = "st,stm32f7-i2c";
328 #address-cells = <1>;
329 #size-cells = <0>;
334 compatible = "st,stm32f7-i2c";
340 #address-cells = <1>;
341 #size-cells = <0>;
346 compatible = "st,stm32f7-i2c";
352 #address-cells = <1>;
353 #size-cells = <0>;
358 compatible = "st,stm32f4-bxcan";
361 interrupt-names = "tx", "rx0", "rx1", "sce";
364 st,can-primary;
370 compatible = "st,stm32f4-gcan", "syscon";
376 compatible = "st,stm32f4-bxcan";
379 interrupt-names = "tx", "rx0", "rx1", "sce";
382 st,can-secondary;
388 compatible = "st,stm32-cec";
392 clock-names = "cec", "hdmi-cec";
397 compatible = "st,stm32f7-uart";
405 compatible = "st,stm32f7-uart";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 compatible = "st,stm32-timers";
418 clock-names = "int";
421 pwm {
422 compatible = "st,stm32-pwm";
423 #pwm-cells = <3>;
428 compatible = "st,stm32-timer-trigger";
435 #address-cells = <1>;
436 #size-cells = <0>;
437 compatible = "st,stm32-timers";
440 clock-names = "int";
443 pwm {
444 compatible = "st,stm32-pwm";
445 #pwm-cells = <3>;
450 compatible = "st,stm32-timer-trigger";
457 compatible = "st,stm32f7-uart";
465 compatible = "st,stm32f7-uart";
474 arm,primecell-periphid = <0x00880180>;
477 clock-names = "apb_pclk";
479 max-frequency = <48000000>;
485 arm,primecell-periphid = <0x00880180>;
488 clock-names = "apb_pclk";
490 max-frequency = <48000000>;
495 compatible = "st,stm32-syscfg", "syscon";
499 exti: interrupt-controller@40013c00 {
500 compatible = "st,stm32-exti";
501 interrupt-controller;
502 #interrupt-cells = <2>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510 compatible = "st,stm32-timers";
513 clock-names = "int";
516 pwm {
517 compatible = "st,stm32-pwm";
518 #pwm-cells = <3>;
523 compatible = "st,stm32-timer-trigger";
530 compatible = "st,stm32-timers";
533 clock-names = "int";
536 pwm {
537 compatible = "st,stm32-pwm";
538 #pwm-cells = <3>;
544 compatible = "st,stm32-timers";
547 clock-names = "int";
550 pwm {
551 compatible = "st,stm32-pwm";
552 #pwm-cells = <3>;
557 ltdc: display-controller@40016800 {
558 compatible = "st,stm32-ltdc";
563 clock-names = "lcd";
567 pwrcfg: power-config@40007000 {
568 compatible = "st,stm32-power-config", "syscon";
573 compatible = "st,stm32f7-crc";
580 #reset-cells = <1>;
581 #clock-cells = <2>;
582 compatible = "st,stm32f746-rcc", "st,stm32-rcc";
586 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
587 assigned-clock-rates = <1000000>;
590 dma1: dma-controller@40026000 {
591 compatible = "st,stm32-dma";
602 #dma-cells = <4>;
606 dma2: dma-controller@40026400 {
607 compatible = "st,stm32-dma";
618 #dma-cells = <4>;
624 compatible = "st,stm32f7-hsotg";
628 clock-names = "otg";
629 g-rx-fifo-size = <256>;
630 g-np-tx-fifo-size = <32>;
631 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
636 compatible = "st,stm32f4x9-fsotg";
640 clock-names = "otg";