Lines Matching +full:rk3188 +full:- +full:i2c
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 #include <dt-bindings/interrupt-controller/irq.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
9 #include <dt-bindings/soc/rockchip,boot-mode.h>
12 #address-cells = <1>;
13 #size-cells = <1>;
15 interrupt-parent = <&gic>;
33 compatible = "fixed-clock";
34 clock-frequency = <24000000>;
35 #clock-cells = <0>;
36 clock-output-names = "xin24m";
40 compatible = "arm,mali-400";
43 clock-names = "bus", "core";
44 assigned-clocks = <&cru ACLK_GPU>;
45 assigned-clock-rates = <100000000>;
50 vpu: video-codec@10104000 {
51 compatible = "rockchip,rk3066-vpu";
55 interrupt-names = "vepu", "vdpu";
58 clock-names = "aclk_vdpu", "hclk_vdpu",
62 L2: cache-controller@10138000 {
63 compatible = "arm,pl310-cache";
65 cache-unified;
66 cache-level = <2>;
70 compatible = "arm,cortex-a9-scu";
74 global_timer: global-timer@1013c200 {
75 compatible = "arm,cortex-a9-global-timer";
81 * on Rockchip rk3066a/rk3188 are quite unstable because their rates
84 * DW_APB_TIMER (rk3066a) or ROCKCHIP_TIMER (rk3188) selected by default.
88 local_timer: local-timer@1013c600 {
89 compatible = "arm,cortex-a9-twd-timer";
95 gic: interrupt-controller@1013d000 {
96 compatible = "arm,cortex-a9-gic";
97 interrupt-controller;
98 #interrupt-cells = <3>;
104 compatible = "snps,dw-apb-uart";
107 reg-shift = <2>;
108 reg-io-width = <1>;
109 clock-names = "baudclk", "apb_pclk";
115 compatible = "snps,dw-apb-uart";
118 reg-shift = <2>;
119 reg-io-width = <1>;
120 clock-names = "baudclk", "apb_pclk";
126 compatible = "rockchip,rk3066-qos", "syscon";
131 compatible = "rockchip,rk3066-qos", "syscon";
136 compatible = "rockchip,rk3066-qos", "syscon";
141 compatible = "rockchip,rk3066-qos", "syscon";
146 compatible = "rockchip,rk3066-qos", "syscon";
151 compatible = "rockchip,rk3066-qos", "syscon";
156 compatible = "rockchip,rk3066-qos", "syscon";
161 compatible = "rockchip,rk3066-qos", "syscon";
166 compatible = "rockchip,rk3066-usb", "snps,dwc2";
170 clock-names = "otg";
172 g-np-tx-fifo-size = <16>;
173 g-rx-fifo-size = <275>;
174 g-tx-fifo-size = <256 128 128 64 64 32>;
176 phy-names = "usb2-phy";
185 clock-names = "otg";
188 phy-names = "usb2-phy";
193 compatible = "snps,arc-emac";
200 clock-names = "hclk", "macref";
201 max-speed = <100>;
202 phy-mode = "rmii";
208 compatible = "rockchip,rk2928-dw-mshc";
212 clock-names = "biu", "ciu";
214 dma-names = "rx-tx";
215 fifo-depth = <256>;
217 reset-names = "reset";
222 compatible = "rockchip,rk2928-dw-mshc";
226 clock-names = "biu", "ciu";
228 dma-names = "rx-tx";
229 fifo-depth = <256>;
231 reset-names = "reset";
236 compatible = "rockchip,rk2928-dw-mshc";
240 clock-names = "biu", "ciu";
242 dma-names = "rx-tx";
243 fifo-depth = <256>;
245 reset-names = "reset";
249 nfc: nand-controller@10500000 {
250 compatible = "rockchip,rk2928-nfc";
254 clock-names = "ahb";
259 compatible = "rockchip,rk3066-pmu", "syscon", "simple-mfd";
262 reboot-mode {
263 compatible = "syscon-reboot-mode";
265 mode-normal = <BOOT_NORMAL>;
266 mode-recovery = <BOOT_RECOVERY>;
267 mode-bootloader = <BOOT_FASTBOOT>;
268 mode-loader = <BOOT_BL_DOWNLOAD>;
273 compatible = "syscon", "simple-mfd";
277 dmac1_s: dma-controller@20018000 {
282 #dma-cells = <1>;
283 arm,pl330-broken-no-flushp;
284 arm,pl330-periph-burst;
286 clock-names = "apb_pclk";
289 dmac1_ns: dma-controller@2001c000 {
294 #dma-cells = <1>;
295 arm,pl330-broken-no-flushp;
296 arm,pl330-periph-burst;
298 clock-names = "apb_pclk";
302 i2c0: i2c@2002d000 {
303 compatible = "rockchip,rk3066-i2c";
306 #address-cells = <1>;
307 #size-cells = <0>;
311 clock-names = "i2c";
317 i2c1: i2c@2002f000 {
318 compatible = "rockchip,rk3066-i2c";
321 #address-cells = <1>;
322 #size-cells = <0>;
327 clock-names = "i2c";
333 compatible = "rockchip,rk2928-pwm";
335 #pwm-cells = <2>;
341 compatible = "rockchip,rk2928-pwm";
343 #pwm-cells = <2>;
349 compatible = "snps,dw-wdt";
357 compatible = "rockchip,rk2928-pwm";
359 #pwm-cells = <2>;
365 compatible = "rockchip,rk2928-pwm";
367 #pwm-cells = <2>;
372 i2c2: i2c@20056000 {
373 compatible = "rockchip,rk3066-i2c";
376 #address-cells = <1>;
377 #size-cells = <0>;
382 clock-names = "i2c";
387 i2c3: i2c@2005a000 {
388 compatible = "rockchip,rk3066-i2c";
391 #address-cells = <1>;
392 #size-cells = <0>;
397 clock-names = "i2c";
402 i2c4: i2c@2005e000 {
403 compatible = "rockchip,rk3066-i2c";
406 #address-cells = <1>;
407 #size-cells = <0>;
412 clock-names = "i2c";
418 compatible = "snps,dw-apb-uart";
421 reg-shift = <2>;
422 reg-io-width = <1>;
423 clock-names = "baudclk", "apb_pclk";
429 compatible = "snps,dw-apb-uart";
432 reg-shift = <2>;
433 reg-io-width = <1>;
434 clock-names = "baudclk", "apb_pclk";
443 #io-channel-cells = <1>;
445 clock-names = "saradc", "apb_pclk";
447 reset-names = "saradc-apb";
452 compatible = "rockchip,rk3066-spi";
454 clock-names = "spiclk", "apb_pclk";
457 #address-cells = <1>;
458 #size-cells = <0>;
460 dma-names = "tx", "rx";
465 compatible = "rockchip,rk3066-spi";
467 clock-names = "spiclk", "apb_pclk";
470 #address-cells = <1>;
471 #size-cells = <0>;
473 dma-names = "tx", "rx";
477 dmac2: dma-controller@20078000 {
482 #dma-cells = <1>;
483 arm,pl330-broken-no-flushp;
484 arm,pl330-periph-burst;
486 clock-names = "apb_pclk";