Lines Matching +full:ciu +full:- +full:drive
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/interrupt-controller/irq.h>
5 #include <dt-bindings/interrupt-controller/arm-gic.h>
6 #include <dt-bindings/pinctrl/rockchip.h>
7 #include <dt-bindings/clock/rk3288-cru.h>
8 #include <dt-bindings/power/rk3288-power.h>
9 #include <dt-bindings/thermal/thermal.h>
10 #include <dt-bindings/soc/rockchip,boot-mode.h>
13 #address-cells = <2>;
14 #size-cells = <2>;
18 interrupt-parent = <&gic>;
42 arm-pmu {
43 compatible = "arm,cortex-a12-pmu";
48 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
52 #address-cells = <1>;
53 #size-cells = <0>;
54 enable-method = "rockchip,rk3066-smp";
59 compatible = "arm,cortex-a12";
62 operating-points-v2 = <&cpu_opp_table>;
63 #cooling-cells = <2>; /* min followed by max */
64 clock-latency = <40000>;
66 dynamic-power-coefficient = <370>;
70 compatible = "arm,cortex-a12";
73 operating-points-v2 = <&cpu_opp_table>;
74 #cooling-cells = <2>; /* min followed by max */
75 clock-latency = <40000>;
77 dynamic-power-coefficient = <370>;
81 compatible = "arm,cortex-a12";
84 operating-points-v2 = <&cpu_opp_table>;
85 #cooling-cells = <2>; /* min followed by max */
86 clock-latency = <40000>;
88 dynamic-power-coefficient = <370>;
92 compatible = "arm,cortex-a12";
95 operating-points-v2 = <&cpu_opp_table>;
96 #cooling-cells = <2>; /* min followed by max */
97 clock-latency = <40000>;
99 dynamic-power-coefficient = <370>;
103 cpu_opp_table: opp-table-0 {
104 compatible = "operating-points-v2";
105 opp-shared;
107 opp-126000000 {
108 opp-hz = /bits/ 64 <126000000>;
109 opp-microvolt = <900000>;
111 opp-216000000 {
112 opp-hz = /bits/ 64 <216000000>;
113 opp-microvolt = <900000>;
115 opp-312000000 {
116 opp-hz = /bits/ 64 <312000000>;
117 opp-microvolt = <900000>;
119 opp-408000000 {
120 opp-hz = /bits/ 64 <408000000>;
121 opp-microvolt = <900000>;
123 opp-600000000 {
124 opp-hz = /bits/ 64 <600000000>;
125 opp-microvolt = <900000>;
127 opp-696000000 {
128 opp-hz = /bits/ 64 <696000000>;
129 opp-microvolt = <950000>;
131 opp-816000000 {
132 opp-hz = /bits/ 64 <816000000>;
133 opp-microvolt = <1000000>;
135 opp-1008000000 {
136 opp-hz = /bits/ 64 <1008000000>;
137 opp-microvolt = <1050000>;
139 opp-1200000000 {
140 opp-hz = /bits/ 64 <1200000000>;
141 opp-microvolt = <1100000>;
143 opp-1416000000 {
144 opp-hz = /bits/ 64 <1416000000>;
145 opp-microvolt = <1200000>;
147 opp-1512000000 {
148 opp-hz = /bits/ 64 <1512000000>;
149 opp-microvolt = <1300000>;
151 opp-1608000000 {
152 opp-hz = /bits/ 64 <1608000000>;
153 opp-microvolt = <1350000>;
157 reserved-memory {
158 #address-cells = <2>;
159 #size-cells = <2>;
172 dma-unusable@fe000000 {
178 compatible = "fixed-clock";
179 clock-frequency = <24000000>;
180 clock-output-names = "xin24m";
181 #clock-cells = <0>;
185 compatible = "arm,armv7-timer";
186 arm,cpu-registers-not-fw-configured;
191 clock-frequency = <24000000>;
192 arm,no-tick-in-suspend;
196 compatible = "rockchip,rk3288-timer";
200 clock-names = "pclk", "timer";
203 display-subsystem {
204 compatible = "rockchip,display-subsystem";
209 compatible = "rockchip,rk3288-dw-mshc";
210 max-frequency = <150000000>;
213 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
214 fifo-depth = <0x100>;
218 reset-names = "reset";
223 compatible = "rockchip,rk3288-dw-mshc";
224 max-frequency = <150000000>;
227 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
228 fifo-depth = <0x100>;
232 reset-names = "reset";
237 compatible = "rockchip,rk3288-dw-mshc";
238 max-frequency = <150000000>;
241 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
242 fifo-depth = <0x100>;
246 reset-names = "reset";
251 compatible = "rockchip,rk3288-dw-mshc";
252 max-frequency = <150000000>;
255 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
256 fifo-depth = <0x100>;
260 reset-names = "reset";
268 #io-channel-cells = <1>;
270 clock-names = "saradc", "apb_pclk";
272 reset-names = "saradc-apb";
277 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
279 clock-names = "spiclk", "apb_pclk";
281 dma-names = "tx", "rx";
283 pinctrl-names = "default";
284 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
286 #address-cells = <1>;
287 #size-cells = <0>;
292 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
294 clock-names = "spiclk", "apb_pclk";
296 dma-names = "tx", "rx";
298 pinctrl-names = "default";
299 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
301 #address-cells = <1>;
302 #size-cells = <0>;
307 compatible = "rockchip,rk3288-spi", "rockchip,rk3066-spi";
309 clock-names = "spiclk", "apb_pclk";
311 dma-names = "tx", "rx";
313 pinctrl-names = "default";
314 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
316 #address-cells = <1>;
317 #size-cells = <0>;
322 compatible = "rockchip,rk3288-i2c";
325 #address-cells = <1>;
326 #size-cells = <0>;
327 clock-names = "i2c";
329 pinctrl-names = "default";
330 pinctrl-0 = <&i2c1_xfer>;
335 compatible = "rockchip,rk3288-i2c";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 clock-names = "i2c";
342 pinctrl-names = "default";
343 pinctrl-0 = <&i2c3_xfer>;
348 compatible = "rockchip,rk3288-i2c";
351 #address-cells = <1>;
352 #size-cells = <0>;
353 clock-names = "i2c";
355 pinctrl-names = "default";
356 pinctrl-0 = <&i2c4_xfer>;
361 compatible = "rockchip,rk3288-i2c";
364 #address-cells = <1>;
365 #size-cells = <0>;
366 clock-names = "i2c";
368 pinctrl-names = "default";
369 pinctrl-0 = <&i2c5_xfer>;
374 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
377 reg-shift = <2>;
378 reg-io-width = <4>;
380 clock-names = "baudclk", "apb_pclk";
382 dma-names = "tx", "rx";
383 pinctrl-names = "default";
384 pinctrl-0 = <&uart0_xfer>;
389 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
392 reg-shift = <2>;
393 reg-io-width = <4>;
395 clock-names = "baudclk", "apb_pclk";
397 dma-names = "tx", "rx";
398 pinctrl-names = "default";
399 pinctrl-0 = <&uart1_xfer>;
404 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
407 reg-shift = <2>;
408 reg-io-width = <4>;
410 clock-names = "baudclk", "apb_pclk";
411 pinctrl-names = "default";
412 pinctrl-0 = <&uart2_xfer>;
417 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
420 reg-shift = <2>;
421 reg-io-width = <4>;
423 clock-names = "baudclk", "apb_pclk";
425 dma-names = "tx", "rx";
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart3_xfer>;
432 compatible = "rockchip,rk3288-uart", "snps,dw-apb-uart";
435 reg-shift = <2>;
436 reg-io-width = <4>;
438 clock-names = "baudclk", "apb_pclk";
440 dma-names = "tx", "rx";
441 pinctrl-names = "default";
442 pinctrl-0 = <&uart4_xfer>;
446 dmac_peri: dma-controller@ff250000 {
451 #dma-cells = <1>;
452 arm,pl330-broken-no-flushp;
453 arm,pl330-periph-burst;
455 clock-names = "apb_pclk";
458 thermal-zones {
459 reserve_thermal: reserve-thermal {
460 polling-delay-passive = <1000>; /* milliseconds */
461 polling-delay = <5000>; /* milliseconds */
463 thermal-sensors = <&tsadc 0>;
466 cpu_thermal: cpu-thermal {
467 polling-delay-passive = <100>; /* milliseconds */
468 polling-delay = <5000>; /* milliseconds */
470 thermal-sensors = <&tsadc 1>;
490 cooling-maps {
493 cooling-device =
501 cooling-device =
510 gpu_thermal: gpu-thermal {
511 polling-delay-passive = <100>; /* milliseconds */
512 polling-delay = <5000>; /* milliseconds */
514 thermal-sensors = <&tsadc 2>;
529 cooling-maps {
532 cooling-device =
540 compatible = "rockchip,rk3288-tsadc";
544 clock-names = "tsadc", "apb_pclk";
546 reset-names = "tsadc-apb";
547 pinctrl-names = "init", "default", "sleep";
548 pinctrl-0 = <&otp_pin>;
549 pinctrl-1 = <&otp_out>;
550 pinctrl-2 = <&otp_pin>;
551 #thermal-sensor-cells = <1>;
553 rockchip,hw-tshut-temp = <95000>;
558 compatible = "rockchip,rk3288-gmac";
562 interrupt-names = "macirq", "eth_wake_irq";
568 clock-names = "stmmaceth",
573 reset-names = "stmmaceth";
578 compatible = "generic-ehci";
583 phy-names = "usb";
589 compatible = "generic-ohci";
594 phy-names = "usb";
599 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
604 clock-names = "otg";
607 phy-names = "usb2-phy";
608 snps,reset-phy-on-wake;
613 compatible = "rockchip,rk3288-usb", "rockchip,rk3066-usb",
618 clock-names = "otg";
620 g-np-tx-fifo-size = <16>;
621 g-rx-fifo-size = <275>;
622 g-tx-fifo-size = <256 128 128 64 64 32>;
624 phy-names = "usb2-phy";
629 compatible = "generic-ehci";
636 dmac_bus_ns: dma-controller@ff600000 {
641 #dma-cells = <1>;
642 arm,pl330-broken-no-flushp;
643 arm,pl330-periph-burst;
645 clock-names = "apb_pclk";
650 compatible = "rockchip,rk3288-i2c";
653 #address-cells = <1>;
654 #size-cells = <0>;
655 clock-names = "i2c";
657 pinctrl-names = "default";
658 pinctrl-0 = <&i2c0_xfer>;
663 compatible = "rockchip,rk3288-i2c";
666 #address-cells = <1>;
667 #size-cells = <0>;
668 clock-names = "i2c";
670 pinctrl-names = "default";
671 pinctrl-0 = <&i2c2_xfer>;
676 compatible = "rockchip,rk3288-pwm";
678 #pwm-cells = <3>;
679 pinctrl-names = "default";
680 pinctrl-0 = <&pwm0_pin>;
686 compatible = "rockchip,rk3288-pwm";
688 #pwm-cells = <3>;
689 pinctrl-names = "default";
690 pinctrl-0 = <&pwm1_pin>;
696 compatible = "rockchip,rk3288-pwm";
698 #pwm-cells = <3>;
699 pinctrl-names = "default";
700 pinctrl-0 = <&pwm2_pin>;
706 compatible = "rockchip,rk3288-pwm";
708 #pwm-cells = <3>;
709 pinctrl-names = "default";
710 pinctrl-0 = <&pwm3_pin>;
716 compatible = "mmio-sram";
718 #address-cells = <1>;
719 #size-cells = <1>;
721 smp-sram@0 {
722 compatible = "rockchip,rk3066-smp-sram";
728 compatible = "rockchip,rk3288-pmu-sram", "mmio-sram";
732 pmu: power-management@ff730000 {
733 compatible = "rockchip,rk3288-pmu", "syscon", "simple-mfd";
736 power: power-controller {
737 compatible = "rockchip,rk3288-power-controller";
738 #power-domain-cells = <1>;
739 #address-cells = <1>;
740 #size-cells = <0>;
742 assigned-clocks = <&cru SCLK_EDP_24M>;
743 assigned-clock-parents = <&xin24m>;
768 power-domain@RK3288_PD_VIO {
804 #power-domain-cells = <0>;
811 power-domain@RK3288_PD_HEVC {
818 #power-domain-cells = <0>;
826 power-domain@RK3288_PD_VIDEO {
831 #power-domain-cells = <0>;
838 power-domain@RK3288_PD_GPU {
843 #power-domain-cells = <0>;
847 reboot-mode {
848 compatible = "syscon-reboot-mode";
850 mode-normal = <BOOT_NORMAL>;
851 mode-recovery = <BOOT_RECOVERY>;
852 mode-bootloader = <BOOT_FASTBOOT>;
853 mode-loader = <BOOT_BL_DOWNLOAD>;
858 compatible = "rockchip,rk3288-sgrf", "syscon";
862 cru: clock-controller@ff760000 {
863 compatible = "rockchip,rk3288-cru";
866 clock-names = "xin24m";
868 #clock-cells = <1>;
869 #reset-cells = <1>;
870 assigned-clocks = <&cru PLL_GPLL>, <&cru PLL_CPLL>,
875 assigned-clock-rates = <594000000>, <400000000>,
883 compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd";
886 edp_phy: edp-phy {
887 compatible = "rockchip,rk3288-dp-phy";
889 clock-names = "24m";
890 #phy-cells = <0>;
894 io_domains: io-domains {
895 compatible = "rockchip,rk3288-io-voltage-domain";
900 compatible = "rockchip,rk3288-usb-phy";
901 #address-cells = <1>;
902 #size-cells = <0>;
905 usbphy0: usb-phy@320 {
906 #phy-cells = <0>;
909 clock-names = "phyclk";
910 #clock-cells = <0>;
912 reset-names = "phy-reset";
915 usbphy1: usb-phy@334 {
916 #phy-cells = <0>;
919 clock-names = "phyclk";
920 #clock-cells = <0>;
922 reset-names = "phy-reset";
925 usbphy2: usb-phy@348 {
926 #phy-cells = <0>;
929 clock-names = "phyclk";
930 #clock-cells = <0>;
932 reset-names = "phy-reset";
938 compatible = "rockchip,rk3288-wdt", "snps,dw-wdt";
946 compatible = "rockchip,rk3288-spdif", "rockchip,rk3066-spdif";
948 #sound-dai-cells = <0>;
950 clock-names = "mclk", "hclk";
952 dma-names = "tx";
954 pinctrl-names = "default";
955 pinctrl-0 = <&spdif_tx>;
961 compatible = "rockchip,rk3288-i2s", "rockchip,rk3066-i2s";
963 #sound-dai-cells = <0>;
966 clock-names = "i2s_clk", "i2s_hclk";
968 dma-names = "tx", "rx";
969 pinctrl-names = "default";
970 pinctrl-0 = <&i2s0_bus>;
971 rockchip,playback-channels = <8>;
972 rockchip,capture-channels = <2>;
977 compatible = "rockchip,rk3288-crypto";
982 clock-names = "aclk", "hclk", "sclk", "apb_pclk";
984 reset-names = "crypto-rst";
992 clock-names = "aclk", "iface";
993 #iommu-cells = <0>;
1002 clock-names = "aclk", "iface";
1003 #iommu-cells = <0>;
1004 rockchip,disable-mmu-reset;
1009 compatible = "rockchip,rk3288-rga";
1013 clock-names = "aclk", "hclk", "sclk";
1014 power-domains = <&power RK3288_PD_VIO>;
1016 reset-names = "core", "axi", "ahb";
1020 compatible = "rockchip,rk3288-vop";
1024 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1025 power-domains = <&power RK3288_PD_VIO>;
1027 reset-names = "axi", "ahb", "dclk";
1032 #address-cells = <1>;
1033 #size-cells = <0>;
1037 remote-endpoint = <&hdmi_in_vopb>;
1042 remote-endpoint = <&edp_in_vopb>;
1047 remote-endpoint = <&mipi_in_vopb>;
1052 remote-endpoint = <&lvds_in_vopb>;
1062 clock-names = "aclk", "iface";
1063 power-domains = <&power RK3288_PD_VIO>;
1064 #iommu-cells = <0>;
1069 compatible = "rockchip,rk3288-vop";
1073 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1074 power-domains = <&power RK3288_PD_VIO>;
1076 reset-names = "axi", "ahb", "dclk";
1081 #address-cells = <1>;
1082 #size-cells = <0>;
1086 remote-endpoint = <&hdmi_in_vopl>;
1091 remote-endpoint = <&edp_in_vopl>;
1096 remote-endpoint = <&mipi_in_vopl>;
1101 remote-endpoint = <&lvds_in_vopl>;
1111 clock-names = "aclk", "iface";
1112 power-domains = <&power RK3288_PD_VIO>;
1113 #iommu-cells = <0>;
1118 compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
1122 clock-names = "ref", "pclk";
1123 power-domains = <&power RK3288_PD_VIO>;
1128 #address-cells = <1>;
1129 #size-cells = <0>;
1133 #address-cells = <1>;
1134 #size-cells = <0>;
1138 remote-endpoint = <&vopb_out_mipi>;
1143 remote-endpoint = <&vopl_out_mipi>;
1154 compatible = "rockchip,rk3288-lvds";
1157 clock-names = "pclk_lvds";
1158 pinctrl-names = "lcdc";
1159 pinctrl-0 = <&lcdc_ctl>;
1160 power-domains = <&power RK3288_PD_VIO>;
1165 #address-cells = <1>;
1166 #size-cells = <0>;
1170 #address-cells = <1>;
1171 #size-cells = <0>;
1175 remote-endpoint = <&vopb_out_lvds>;
1180 remote-endpoint = <&vopl_out_lvds>;
1191 compatible = "rockchip,rk3288-dp";
1195 clock-names = "dp", "pclk";
1197 phy-names = "dp";
1198 power-domains = <&power RK3288_PD_VIO>;
1200 reset-names = "dp";
1205 #address-cells = <1>;
1206 #size-cells = <0>;
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1215 remote-endpoint = <&vopb_out_edp>;
1220 remote-endpoint = <&vopl_out_edp>;
1231 compatible = "rockchip,rk3288-dw-hdmi";
1233 reg-io-width = <4>;
1234 #sound-dai-cells = <0>;
1238 clock-names = "iahb", "isfr", "cec";
1239 power-domains = <&power RK3288_PD_VIO>;
1244 #address-cells = <1>;
1245 #size-cells = <0>;
1248 remote-endpoint = <&vopb_out_hdmi>;
1252 remote-endpoint = <&vopl_out_hdmi>;
1258 vpu: video-codec@ff9a0000 {
1259 compatible = "rockchip,rk3288-vpu";
1263 interrupt-names = "vepu", "vdpu";
1265 clock-names = "aclk", "hclk";
1267 power-domains = <&power RK3288_PD_VIDEO>;
1275 clock-names = "aclk", "iface";
1276 #iommu-cells = <0>;
1277 power-domains = <&power RK3288_PD_VIDEO>;
1285 clock-names = "aclk", "iface";
1286 #iommu-cells = <0>;
1291 compatible = "rockchip,rk3288-mali", "arm,mali-t760";
1296 interrupt-names = "job", "mmu", "gpu";
1298 operating-points-v2 = <&gpu_opp_table>;
1299 #cooling-cells = <2>; /* min followed by max */
1300 power-domains = <&power RK3288_PD_GPU>;
1304 gpu_opp_table: opp-table-1 {
1305 compatible = "operating-points-v2";
1307 opp-100000000 {
1308 opp-hz = /bits/ 64 <100000000>;
1309 opp-microvolt = <950000>;
1311 opp-200000000 {
1312 opp-hz = /bits/ 64 <200000000>;
1313 opp-microvolt = <950000>;
1315 opp-300000000 {
1316 opp-hz = /bits/ 64 <300000000>;
1317 opp-microvolt = <1000000>;
1319 opp-400000000 {
1320 opp-hz = /bits/ 64 <400000000>;
1321 opp-microvolt = <1100000>;
1323 opp-600000000 {
1324 opp-hz = /bits/ 64 <600000000>;
1325 opp-microvolt = <1250000>;
1330 compatible = "rockchip,rk3288-qos", "syscon";
1335 compatible = "rockchip,rk3288-qos", "syscon";
1340 compatible = "rockchip,rk3288-qos", "syscon";
1345 compatible = "rockchip,rk3288-qos", "syscon";
1350 compatible = "rockchip,rk3288-qos", "syscon";
1355 compatible = "rockchip,rk3288-qos", "syscon";
1360 compatible = "rockchip,rk3288-qos", "syscon";
1365 compatible = "rockchip,rk3288-qos", "syscon";
1370 compatible = "rockchip,rk3288-qos", "syscon";
1375 compatible = "rockchip,rk3288-qos", "syscon";
1380 compatible = "rockchip,rk3288-qos", "syscon";
1385 compatible = "rockchip,rk3288-qos", "syscon";
1390 compatible = "rockchip,rk3288-qos", "syscon";
1395 compatible = "rockchip,rk3288-qos", "syscon";
1399 dmac_bus_s: dma-controller@ffb20000 {
1404 #dma-cells = <1>;
1405 arm,pl330-broken-no-flushp;
1406 arm,pl330-periph-burst;
1408 clock-names = "apb_pclk";
1412 compatible = "rockchip,rk3288-efuse";
1414 #address-cells = <1>;
1415 #size-cells = <1>;
1417 clock-names = "pclk_efuse";
1419 cpu_id: cpu-id@7 {
1427 gic: interrupt-controller@ffc01000 {
1428 compatible = "arm,gic-400";
1429 interrupt-controller;
1430 #interrupt-cells = <3>;
1431 #address-cells = <0>;
1441 compatible = "rockchip,rk3288-pinctrl";
1444 #address-cells = <2>;
1445 #size-cells = <2>;
1449 compatible = "rockchip,gpio-bank";
1454 gpio-controller;
1455 #gpio-cells = <2>;
1457 interrupt-controller;
1458 #interrupt-cells = <2>;
1462 compatible = "rockchip,gpio-bank";
1467 gpio-controller;
1468 #gpio-cells = <2>;
1470 interrupt-controller;
1471 #interrupt-cells = <2>;
1475 compatible = "rockchip,gpio-bank";
1480 gpio-controller;
1481 #gpio-cells = <2>;
1483 interrupt-controller;
1484 #interrupt-cells = <2>;
1488 compatible = "rockchip,gpio-bank";
1493 gpio-controller;
1494 #gpio-cells = <2>;
1496 interrupt-controller;
1497 #interrupt-cells = <2>;
1501 compatible = "rockchip,gpio-bank";
1506 gpio-controller;
1507 #gpio-cells = <2>;
1509 interrupt-controller;
1510 #interrupt-cells = <2>;
1514 compatible = "rockchip,gpio-bank";
1519 gpio-controller;
1520 #gpio-cells = <2>;
1522 interrupt-controller;
1523 #interrupt-cells = <2>;
1527 compatible = "rockchip,gpio-bank";
1532 gpio-controller;
1533 #gpio-cells = <2>;
1535 interrupt-controller;
1536 #interrupt-cells = <2>;
1540 compatible = "rockchip,gpio-bank";
1545 gpio-controller;
1546 #gpio-cells = <2>;
1548 interrupt-controller;
1549 #interrupt-cells = <2>;
1553 compatible = "rockchip,gpio-bank";
1558 gpio-controller;
1559 #gpio-cells = <2>;
1561 interrupt-controller;
1562 #interrupt-cells = <2>;
1566 hdmi_cec_c0: hdmi-cec-c0 {
1570 hdmi_cec_c7: hdmi-cec-c7 {
1574 hdmi_ddc: hdmi-ddc {
1579 hdmi_ddc_unwedge: hdmi-ddc-unwedge {
1585 pcfg_output_low: pcfg-output-low {
1586 output-low;
1589 pcfg_pull_up: pcfg-pull-up {
1590 bias-pull-up;
1593 pcfg_pull_down: pcfg-pull-down {
1594 bias-pull-down;
1597 pcfg_pull_none: pcfg-pull-none {
1598 bias-disable;
1601 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
1602 bias-disable;
1603 drive-strength = <12>;
1607 global_pwroff: global-pwroff {
1611 ddrio_pwroff: ddrio-pwroff {
1615 ddr0_retention: ddr0-retention {
1619 ddr1_retention: ddr1-retention {
1625 edp_hpd: edp-hpd {
1631 i2c0_xfer: i2c0-xfer {
1638 i2c1_xfer: i2c1-xfer {
1645 i2c2_xfer: i2c2-xfer {
1652 i2c3_xfer: i2c3-xfer {
1659 i2c4_xfer: i2c4-xfer {
1666 i2c5_xfer: i2c5-xfer {
1673 i2s0_bus: i2s0-bus {
1684 lcdc_ctl: lcdc-ctl {
1693 sdmmc_clk: sdmmc-clk {
1697 sdmmc_cmd: sdmmc-cmd {
1701 sdmmc_cd: sdmmc-cd {
1705 sdmmc_bus1: sdmmc-bus1 {
1709 sdmmc_bus4: sdmmc-bus4 {
1718 sdio0_bus1: sdio0-bus1 {
1722 sdio0_bus4: sdio0-bus4 {
1729 sdio0_cmd: sdio0-cmd {
1733 sdio0_clk: sdio0-clk {
1737 sdio0_cd: sdio0-cd {
1741 sdio0_wp: sdio0-wp {
1745 sdio0_pwr: sdio0-pwr {
1749 sdio0_bkpwr: sdio0-bkpwr {
1753 sdio0_int: sdio0-int {
1759 sdio1_bus1: sdio1-bus1 {
1763 sdio1_bus4: sdio1-bus4 {
1770 sdio1_cd: sdio1-cd {
1774 sdio1_wp: sdio1-wp {
1778 sdio1_bkpwr: sdio1-bkpwr {
1782 sdio1_int: sdio1-int {
1786 sdio1_cmd: sdio1-cmd {
1790 sdio1_clk: sdio1-clk {
1794 sdio1_pwr: sdio1-pwr {
1800 emmc_clk: emmc-clk {
1804 emmc_cmd: emmc-cmd {
1808 emmc_pwr: emmc-pwr {
1812 emmc_bus1: emmc-bus1 {
1816 emmc_bus4: emmc-bus4 {
1823 emmc_bus8: emmc-bus8 {
1836 spi0_clk: spi0-clk {
1839 spi0_cs0: spi0-cs0 {
1842 spi0_tx: spi0-tx {
1845 spi0_rx: spi0-rx {
1848 spi0_cs1: spi0-cs1 {
1853 spi1_clk: spi1-clk {
1856 spi1_cs0: spi1-cs0 {
1859 spi1_rx: spi1-rx {
1862 spi1_tx: spi1-tx {
1868 spi2_cs1: spi2-cs1 {
1871 spi2_clk: spi2-clk {
1874 spi2_cs0: spi2-cs0 {
1877 spi2_rx: spi2-rx {
1880 spi2_tx: spi2-tx {
1886 uart0_xfer: uart0-xfer {
1891 uart0_cts: uart0-cts {
1895 uart0_rts: uart0-rts {
1901 uart1_xfer: uart1-xfer {
1906 uart1_cts: uart1-cts {
1910 uart1_rts: uart1-rts {
1916 uart2_xfer: uart2-xfer {
1924 uart3_xfer: uart3-xfer {
1929 uart3_cts: uart3-cts {
1933 uart3_rts: uart3-rts {
1939 uart4_xfer: uart4-xfer {
1944 uart4_cts: uart4-cts {
1948 uart4_rts: uart4-rts {
1954 otp_pin: otp-pin {
1958 otp_out: otp-out {
1964 pwm0_pin: pwm0-pin {
1970 pwm1_pin: pwm1-pin {
1976 pwm2_pin: pwm2-pin {
1982 pwm3_pin: pwm3-pin {
1988 rgmii_pins: rgmii-pins {
2006 rmii_pins: rmii-pins {
2021 spdif_tx: spdif-tx {