Lines Matching full:cru
6 #include <dt-bindings/clock/rk3128-cru.h>
36 clocks = <&cru ARMCLK>;
101 clocks = <&cru HCLK_OTG>;
131 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
132 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
138 resets = <&cru SRST_SDMMC>;
147 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
148 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
154 resets = <&cru SRST_SDIO>;
163 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
164 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
170 resets = <&cru SRST_EMMC>;
179 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>;
187 cru: clock-controller@20000000 { label
188 compatible = "rockchip,rk3128-cru";
195 assigned-clocks = <&cru PLL_GPLL>;
208 clocks = <&cru SCLK_OTGPHY0>;
237 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
245 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
253 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
261 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
269 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
277 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
285 clocks = <&cru PCLK_WDT>;
292 clocks = <&cru PCLK_PWM>;
302 clocks = <&cru PCLK_PWM>;
312 clocks = <&cru PCLK_PWM>;
322 clocks = <&cru PCLK_PWM>;
334 clocks = <&cru PCLK_I2C1>;
347 clocks = <&cru PCLK_I2C2>;
360 clocks = <&cru PCLK_I2C3>;
373 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
389 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
405 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
420 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
422 resets = <&cru SRST_SARADC>;
433 clocks = <&cru PCLK_I2C0>;
445 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
463 clocks = <&cru ACLK_DMAC>;
479 clocks = <&cru PCLK_GPIO0>;
490 clocks = <&cru PCLK_GPIO1>;
501 clocks = <&cru PCLK_GPIO2>;
512 clocks = <&cru PCLK_GPIO3>;