Lines Matching refs:clocks
27 clocks = <&cpg_clocks SH73A0_CLK_Z>;
36 clocks = <&cpg_clocks SH73A0_CLK_Z>;
46 clocks = <&periph_clk>;
53 clocks = <&periph_clk>;
105 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
128 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
150 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
172 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
194 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
208 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
222 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
236 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
250 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
264 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
274 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
284 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
295 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
306 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
317 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
330 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
342 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
354 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
365 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
375 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
385 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
395 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
405 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
415 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
425 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
435 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
445 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
587 clocks = <&mstp3_clks SH73A0_CLK_FSI>;
600 clocks = <&zb_clk>;
604 clocks {
609 /* External root clocks */
645 /* Special CPG clocks */
647 compatible = "renesas,sh73a0-cpg-clocks";
649 clocks = <&extal1_clk>, <&extal2_clk>;
657 /* Variable factor clocks (DIV6) */
661 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
670 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
679 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
688 clocks = <&pll1_div2_clk>, <0>,
696 clocks = <&pll1_div2_clk>, <0>,
703 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
710 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
717 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
724 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
731 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
738 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
752 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
759 clocks = <&pll1_div2_clk>, <0>,
766 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
773 clocks = <&pll1_div2_clk>, <0>,
780 clocks = <&pll1_div2_clk>, <0>,
787 clocks = <&pll1_div2_clk>, <0>,
794 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
800 /* Fixed factor clocks */
803 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
810 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
817 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
824 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
831 clocks = <&cpg_clocks SH73A0_CLK_Z>;
837 /* Gate clocks */
839 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
841 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
850 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
852 clocks = <&cpg_clocks SH73A0_CLK_B>,
873 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
875 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
897 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
899 clocks = <&sub_clk>, <&extalr_clk>,
925 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
927 clocks = <&cpg_clocks SH73A0_CLK_HP>,
938 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
940 clocks = <&cpg_clocks SH73A0_CLK_HP>;