Lines Matching +full:rcar +full:- +full:gen2 +full:- +full:thermal
1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/r8a73a4-clock.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
15 interrupt-parent = <&gic>;
16 #address-cells = <2>;
17 #size-cells = <2>;
20 #address-cells = <1>;
21 #size-cells = <0>;
25 compatible = "arm,cortex-a15";
28 clock-frequency = <1500000000>;
29 power-domains = <&pd_a2sl>;
30 next-level-cache = <&L2_CA15>;
33 L2_CA15: cache-controller-0 {
36 power-domains = <&pd_a3sm>;
37 cache-unified;
38 cache-level = <2>;
41 L2_CA7: cache-controller-1 {
44 power-domains = <&pd_a3km>;
45 cache-unified;
46 cache-level = <2>;
51 compatible = "arm,coresight-etm3x";
52 power-domains = <&pd_d4>;
56 compatible = "arm,armv7-timer";
63 dbsc1: memory-controller@e6790000 {
64 compatible = "renesas,dbsc-r8a73a4";
66 power-domains = <&pd_a3bc>;
69 dbsc2: memory-controller@e67a0000 {
70 compatible = "renesas,dbsc-r8a73a4";
72 power-domains = <&pd_a3bc>;
76 #address-cells = <1>;
77 #size-cells = <0>;
78 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
82 power-domains = <&pd_a3sp>;
88 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1";
99 clock-names = "fck";
100 power-domains = <&pd_c5>;
104 irqc0: interrupt-controller@e61c0000 {
105 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
106 #interrupt-cells = <2>;
107 interrupt-controller;
142 power-domains = <&pd_c4>;
145 irqc1: interrupt-controller@e61c0200 {
146 compatible = "renesas,irqc-r8a73a4", "renesas,irqc";
147 #interrupt-cells = <2>;
148 interrupt-controller;
177 power-domains = <&pd_c4>;
181 compatible = "renesas,pfc-r8a73a4";
183 gpio-controller;
184 #gpio-cells = <2>;
185 gpio-ranges =
192 interrupts-extended =
208 power-domains = <&pd_c5>;
211 thermal@e61f0000 {
212 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal";
217 power-domains = <&pd_c5>;
221 #address-cells = <1>;
222 #size-cells = <0>;
223 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
227 power-domains = <&pd_a3sp>;
232 #address-cells = <1>;
233 #size-cells = <0>;
234 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
238 power-domains = <&pd_a3sp>;
243 #address-cells = <1>;
244 #size-cells = <0>;
245 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
249 power-domains = <&pd_a3sp>;
254 #address-cells = <1>;
255 #size-cells = <0>;
256 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
260 power-domains = <&pd_a3sp>;
265 #address-cells = <1>;
266 #size-cells = <0>;
267 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
271 power-domains = <&pd_a3sp>;
276 #address-cells = <1>;
277 #size-cells = <0>;
278 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
282 power-domains = <&pd_a3sp>;
287 #address-cells = <1>;
288 #size-cells = <0>;
289 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
293 power-domains = <&pd_a3sp>;
298 #address-cells = <1>;
299 #size-cells = <0>;
300 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic";
304 power-domains = <&pd_a3sp>;
309 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
313 clock-names = "fck";
314 power-domains = <&pd_a3sp>;
319 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
323 clock-names = "fck";
324 power-domains = <&pd_a3sp>;
329 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
333 clock-names = "fck";
334 power-domains = <&pd_a3sp>;
339 compatible = "renesas,scifa-r8a73a4", "renesas,scifa";
343 clock-names = "fck";
344 power-domains = <&pd_a3sp>;
349 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
353 clock-names = "fck";
354 power-domains = <&pd_a3sp>;
359 compatible = "renesas,scifb-r8a73a4", "renesas,scifb";
363 clock-names = "fck";
364 power-domains = <&pd_c4>;
369 compatible = "renesas,sdhi-r8a73a4";
373 power-domains = <&pd_a3sp>;
374 cap-sd-highspeed;
379 compatible = "renesas,sdhi-r8a73a4";
383 power-domains = <&pd_a3sp>;
384 cap-sd-highspeed;
389 compatible = "renesas,sdhi-r8a73a4";
393 power-domains = <&pd_a3sp>;
394 cap-sd-highspeed;
399 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
403 power-domains = <&pd_a3sp>;
404 reg-io-width = <4>;
409 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif";
413 power-domains = <&pd_a3sp>;
414 reg-io-width = <4>;
418 gic: interrupt-controller@f1001000 {
419 compatible = "arm,gic-400";
420 #interrupt-cells = <3>;
421 #address-cells = <0>;
422 interrupt-controller;
429 clock-names = "clk";
430 power-domains = <&pd_c4>;
434 compatible = "renesas,bsc-r8a73a4", "renesas,bsc",
435 "simple-pm-bus";
436 #address-cells = <1>;
437 #size-cells = <1>;
441 power-domains = <&pd_c4>;
445 #address-cells = <2>;
446 #size-cells = <2>;
451 compatible = "fixed-clock";
452 #clock-cells = <0>;
453 clock-frequency = <32768>;
456 compatible = "fixed-clock";
457 #clock-cells = <0>;
458 clock-frequency = <25000000>;
461 compatible = "fixed-clock";
462 #clock-cells = <0>;
463 clock-frequency = <48000000>;
466 compatible = "fixed-clock";
467 #clock-cells = <0>;
469 clock-frequency = <0>;
472 compatible = "fixed-clock";
473 #clock-cells = <0>;
475 clock-frequency = <0>;
480 compatible = "renesas,r8a73a4-cpg-clocks";
483 #clock-cells = <1>;
484 clock-output-names = "main", "pll0", "pll1", "pll2",
492 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
496 #clock-cells = <0>;
497 clock-output-names = "zb";
500 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
504 #clock-cells = <0>;
507 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
511 #clock-cells = <0>;
514 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
518 #clock-cells = <0>;
521 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
525 #clock-cells = <0>;
528 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
532 #clock-cells = <0>;
535 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
540 #clock-cells = <0>;
543 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
548 #clock-cells = <0>;
551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
556 #clock-cells = <0>;
559 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
564 #clock-cells = <0>;
567 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
572 #clock-cells = <0>;
575 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
579 #clock-cells = <0>;
582 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
586 #clock-cells = <0>;
589 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
593 #clock-cells = <0>;
596 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
599 #clock-cells = <0>;
602 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
606 #clock-cells = <0>;
609 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock";
613 #clock-cells = <0>;
618 compatible = "fixed-factor-clock";
620 #clock-cells = <0>;
621 clock-div = <2>;
622 clock-mult = <1>;
625 compatible = "fixed-factor-clock";
627 #clock-cells = <0>;
628 clock-div = <2>;
629 clock-mult = <1>;
632 compatible = "fixed-factor-clock";
634 #clock-cells = <0>;
635 clock-div = <2>;
636 clock-mult = <1>;
639 compatible = "fixed-factor-clock";
641 #clock-cells = <0>;
642 clock-div = <2>;
643 clock-mult = <1>;
648 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
652 #clock-cells = <1>;
653 clock-indices = <
659 clock-output-names =
664 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
672 #clock-cells = <1>;
673 clock-indices = <
681 clock-output-names =
687 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
693 #clock-cells = <1>;
694 clock-indices = <
699 clock-output-names =
700 "irqc", "intc-sys", "iic5", "iic4", "iic3";
703 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks";
706 #clock-cells = <1>;
707 clock-indices = <
710 clock-output-names =
711 "thermal", "iic8";
720 sysc: system-controller@e6180000 {
721 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile";
724 pm-domains {
726 #address-cells = <1>;
727 #size-cells = <0>;
728 #power-domain-cells = <0>;
732 #address-cells = <1>;
733 #size-cells = <0>;
734 #power-domain-cells = <0>;
738 #power-domain-cells = <0>;
743 #power-domain-cells = <0>;
748 #address-cells = <1>;
749 #size-cells = <0>;
750 #power-domain-cells = <0>;
754 #power-domain-cells = <0>;
760 #address-cells = <1>;
761 #size-cells = <0>;
762 #power-domain-cells = <0>;
766 #power-domain-cells = <0>;
772 #address-cells = <1>;
773 #size-cells = <0>;
774 #power-domain-cells = <0>;
778 #power-domain-cells = <0>;
785 #power-domain-cells = <0>;
790 #power-domain-cells = <0>;
795 #power-domain-cells = <0>;
800 #address-cells = <1>;
801 #size-cells = <0>;
802 #power-domain-cells = <0>;
806 #power-domain-cells = <0>;
812 #power-domain-cells = <0>;
817 #power-domain-cells = <0>;
822 #address-cells = <1>;
823 #size-cells = <0>;
824 #power-domain-cells = <0>;
828 #power-domain-cells = <0>;
833 #power-domain-cells = <0>;
839 #power-domain-cells = <0>;
844 #address-cells = <1>;
845 #size-cells = <0>;
846 #power-domain-cells = <0>;
850 #power-domain-cells = <0>;
855 #power-domain-cells = <0>;