Lines Matching refs:gcc
9 #include <dt-bindings/clock/qcom,gcc-sdx65.h>
204 gcc: clock-controller@100000 { label
205 compatible = "qcom,gcc-sdx65";
218 clocks = <&gcc GCC_BLSP1_UART3_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
230 resets = <&gcc GCC_QUSB2PHY_BCR>;
241 clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
242 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
243 <&gcc GCC_USB3_PRIM_CLKREF_EN>;
246 resets = <&gcc GCC_USB3PHY_PHY_BCR>,
247 <&gcc GCC_USB3_PHY_BCR>;
258 clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
316 clocks = <&gcc GCC_PCIE_AUX_CLK>,
317 <&gcc GCC_PCIE_CFG_AHB_CLK>,
318 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
319 <&gcc GCC_PCIE_SLV_AXI_CLK>,
320 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
321 <&gcc GCC_PCIE_SLEEP_CLK>,
322 <&gcc GCC_PCIE_0_CLKREF_EN>;
335 resets = <&gcc GCC_PCIE_BCR>;
338 power-domains = <&gcc PCIE_GDSC>;
353 clocks = <&gcc GCC_PCIE_AUX_PHY_CLK_SRC>,
354 <&gcc GCC_PCIE_CFG_AHB_CLK>,
355 <&gcc GCC_PCIE_0_CLKREF_EN>,
356 <&gcc GCC_PCIE_RCHNG_PHY_CLK>,
357 <&gcc GCC_PCIE_PIPE_CLK>;
364 resets = <&gcc GCC_PCIE_PHY_BCR>;
367 assigned-clocks = <&gcc GCC_PCIE_RCHNG_PHY_CLK>;
370 power-domains = <&gcc PCIE_GDSC>;
469 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
470 <&gcc GCC_SDCC1_AHB_CLK>;
489 clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
490 <&gcc GCC_USB30_MASTER_CLK>,
491 <&gcc GCC_USB30_MSTR_AXI_CLK>,
492 <&gcc GCC_USB30_MOCK_UTMI_CLK>,
493 <&gcc GCC_USB30_SLEEP_CLK>;
497 assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
498 <&gcc GCC_USB30_MASTER_CLK>;
510 power-domains = <&gcc USB30_GDSC>;
512 resets = <&gcc GCC_USB30_BCR>;
644 compatible = "qcom,sdx55-apcs-gcc", "syscon";
647 clocks = <&rpmhcc RPMH_CXO_CLK>, <&a7pll>, <&gcc GPLL0>;