Lines Matching refs:gcc
4 #include <dt-bindings/clock/qcom,gcc-msm8960.h>
6 #include <dt-bindings/reset/qcom,gcc-msm8960.h>
352 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
361 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
370 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
379 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
419 clocks = <&gcc GSBI1_H_CLK>;
432 clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
444 clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
458 clocks = <&gcc GSBI2_H_CLK>;
473 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
486 clocks = <&gcc GSBI3_H_CLK>;
498 clocks = <&gcc GSBI3_QUP_CLK>,
499 <&gcc GSBI3_H_CLK>;
512 clocks = <&gcc GSBI4_H_CLK>;
525 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
537 clocks = <&gcc GSBI4_QUP_CLK>,
538 <&gcc GSBI4_H_CLK>;
549 clocks = <&gcc GSBI5_H_CLK>;
560 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
572 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
585 clocks = <&gcc GSBI6_H_CLK>;
596 clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
608 clocks = <&gcc GSBI6_QUP_CLK>,
609 <&gcc GSBI6_H_CLK>;
620 clocks = <&gcc GSBI7_H_CLK>;
632 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
644 clocks = <&gcc GSBI7_QUP_CLK>,
645 <&gcc GSBI7_H_CLK>;
654 clocks = <&gcc PRNG_CLK>;
801 gcc: clock-controller@900000 { label
802 compatible = "qcom,gcc-apq8064", "syscon";
831 <&gcc PLL4_VOTE>,
853 <&gcc PLL3>,
854 <&gcc PLL8_VOTE>,
871 compatible = "qcom,kpss-gcc-apq8064", "qcom,kpss-gcc", "syscon";
873 clocks = <&gcc PLL8_VOTE>, <&pxo_board>;
955 clocks = <&gcc USB_HS1_XCVR_CLK>, <&gcc USB_HS1_H_CLK>;
957 assigned-clocks = <&gcc USB_HS1_XCVR_CLK>;
959 resets = <&gcc USB_HS1_RESET>;
986 clocks = <&gcc USB_HS3_XCVR_CLK>, <&gcc USB_HS3_H_CLK>;
988 assigned-clocks = <&gcc USB_HS3_XCVR_CLK>;
990 resets = <&gcc USB_HS3_RESET>;
1017 clocks = <&gcc USB_HS4_XCVR_CLK>, <&gcc USB_HS4_H_CLK>;
1019 assigned-clocks = <&gcc USB_HS4_XCVR_CLK>;
1021 resets = <&gcc USB_HS4_RESET>;
1048 clocks = <&gcc SATA_PHY_CFG_CLK>;
1059 clocks = <&gcc SFAB_SATA_S_H_CLK>,
1060 <&gcc SATA_H_CLK>,
1061 <&gcc SATA_A_CLK>,
1062 <&gcc SATA_RXOOB_CLK>,
1063 <&gcc SATA_PMALIVE_CLK>;
1070 assigned-clocks = <&gcc SATA_RXOOB_CLK>,
1071 <&gcc SATA_PMALIVE_CLK>;
1085 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1100 clocks = <&gcc SDC3_H_CLK>;
1112 clocks = <&gcc SDC4_CLK>, <&gcc SDC4_H_CLK>;
1128 clocks = <&gcc SDC4_H_CLK>;
1142 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1157 clocks = <&gcc SDC1_H_CLK>;
1499 clocks = <&gcc PCIE_A_CLK>,
1500 <&gcc PCIE_H_CLK>,
1501 <&gcc PCIE_PHY_REF_CLK>;
1503 resets = <&gcc PCIE_ACLK_RESET>,
1504 <&gcc PCIE_HCLK_RESET>,
1505 <&gcc PCIE_POR_RESET>,
1506 <&gcc PCIE_PCI_RESET>,
1507 <&gcc PCIE_PHY_RESET>;