Lines Matching +full:sck +full:- +full:gpios
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
7 #include "vf610-zii-dev.dtsi"
11 compatible = "zii,vf610dev-c", "zii,vf610dev", "fsl,vf610";
13 mdio-mux {
14 compatible = "mdio-mux-gpio";
15 pinctrl-0 = <&pinctrl_mdio_mux>;
16 pinctrl-names = "default";
17 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH
20 mdio-parent-bus = <&mdio1>;
21 #address-cells = <1>;
22 #size-cells = <0>;
26 #address-cells = <1>;
27 #size-cells = <0>;
31 pinctrl-0 = <&pinctrl_gpio_switch0>;
32 pinctrl-names = "default";
35 eeprom-length = <65536>;
36 interrupt-parent = <&gpio0>;
38 interrupt-controller;
39 #interrupt-cells = <2>;
42 #address-cells = <1>;
43 #size-cells = <0>;
47 phy-mode = "rmii";
50 fixed-link {
52 full-duplex;
59 phy-handle = <&switch0phy1>;
65 phy-handle = <&switch0phy2>;
71 phy-handle = <&switch0phy3>;
77 phy-handle = <&switch0phy4>;
83 phy-mode = "xaui";
86 fixed-link {
88 full-duplex;
94 #address-cells = <1>;
95 #size-cells = <0>;
99 interrupt-parent = <&switch0>;
105 interrupt-parent = <&switch0>;
111 interrupt-parent = <&switch0>;
117 interrupt-parent = <&switch0>;
126 #address-cells = <1>;
127 #size-cells = <0>;
131 pinctrl-0 = <&pinctrl_gpio_switch1>;
132 pinctrl-names = "default";
135 eeprom-length = <65536>;
136 interrupt-parent = <&gpio0>;
138 interrupt-controller;
139 #interrupt-cells = <2>;
142 #address-cells = <1>;
143 #size-cells = <0>;
148 phy-handle = <&switch1phy1>;
154 phy-handle = <&switch1phy2>;
160 phy-handle = <&switch1phy3>;
166 phy-handle = <&switch1phy4>;
172 phy-mode = "1000base-x";
173 managed = "in-band-status";
180 phy-mode = "xaui";
183 fixed-link {
185 full-duplex;
190 #address-cells = <1>;
191 #size-cells = <0>;
195 interrupt-parent = <&switch1>;
201 interrupt-parent = <&switch1>;
207 interrupt-parent = <&switch1>;
213 interrupt-parent = <&switch1>;
222 #address-cells = <1>;
223 #size-cells = <0>;
230 i2c-bus = <&sff2_i2c>;
231 los-gpios = <&gpio6 12 GPIO_ACTIVE_HIGH>;
232 tx-disable-gpios = <&gpio6 14 GPIO_ACTIVE_HIGH>;
238 i2c-bus = <&sff3_i2c>;
239 los-gpios = <&gpio6 13 GPIO_ACTIVE_HIGH>;
240 tx-disable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
245 bus-num = <0>;
246 pinctrl-names = "default";
247 pinctrl-0 = <&pinctrl_dspi0>;
249 spi-num-chipselects = <2>;
252 compatible = "m25p128", "jedec,spi-nor";
253 #address-cells = <1>;
254 #size-cells = <1>;
256 spi-max-frequency = <1000000>;
259 atzb-rf-233@1 {
262 pinctrl-names = "default";
263 pinctrl-0 = <&pinctr_atzb_rf_233>;
265 spi-max-frequency = <7500000>;
268 interrupt-parent = <&gpio3>;
269 xtal-trim = /bits/ 8 <0x06>;
271 sleep-gpio = <&gpio0 24 GPIO_ACTIVE_HIGH>;
272 reset-gpio = <&gpio6 10 GPIO_ACTIVE_LOW>;
274 fsl,spi-cs-sck-delay = <180>;
275 fsl,spi-sck-cs-delay = <250>;
284 * P1 - WE2_CMD
285 * P2 - WE2_CLK
287 gpio5: io-expander@18 {
290 gpio-controller;
291 #gpio-cells = <2>;
298 * I/O0 - ENET_SWR_EN
299 * I/O1 - ESW1_RESETn
300 * I/O2 - ARINC_RESET
301 * I/O3 - DD1_IO_RESET
302 * I/O4 - ESW2_RESETn
303 * I/O5 - ESW3_RESETn
304 * I/O6 - ESW4_RESETn
305 * I/O8 - TP909
306 * I/O9 - FEM_SEL
307 * I/O10 - WIFI_RESETn
308 * I/O11 - PHY_RSTn
309 * I/O12 - OPT1_SD
310 * I/O13 - OPT2_SD
311 * I/O14 - OPT1_TX_DIS
312 * I/O15 - OPT2_TX_DIS
317 pinctrl-names = "default";
318 pinctrl-0 = <&pinctrl_sx1503_20>;
319 #gpio-cells = <2>;
320 #interrupt-cells = <2>;
322 interrupt-parent = <&gpio0>;
324 gpio-controller;
325 interrupt-controller;
332 * IO0 - WE1_CLK
333 * IO1 - WE1_CMD
335 gpio7: io-expander@22 {
338 gpio-controller;
339 #gpio-cells = <2>;
348 read-only;
353 i2c-mux@70 {
355 pinctrl-0 = <&pinctrl_i2c_mux_reset>;
356 pinctrl-names = "default";
357 #address-cells = <1>;
358 #size-cells = <0>;
360 reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
363 #address-cells = <1>;
364 #size-cells = <0>;
369 #address-cells = <1>;
370 #size-cells = <0>;
375 #address-cells = <1>;
376 #size-cells = <0>;
381 #address-cells = <1>;
382 #size-cells = <0>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_uart3>;
396 gpio-hog;
397 gpios = <23 GPIO_ACTIVE_HIGH>;
399 line-name = "sx1503-irq";
405 gpio-hog;
406 gpios = <2 GPIO_ACTIVE_HIGH>;
408 line-name = "eth0-intrp";
414 #address-cells = <1>;
415 #size-cells = <0>;
418 ethernet-phy@0 {
419 compatible = "ethernet-phy-ieee802.3-c22";
421 pinctrl-names = "default";
422 pinctrl-0 = <&pinctrl_fec0_phy_int>;
424 interrupt-parent = <&gpio3>;
432 pinctr_atzb_rf_233: pinctrl-atzb-rf-233 {
440 pinctrl_sx1503_20: pinctrl-sx1503-20 {
453 pinctrl_mdio_mux: pinctrl-mdio-mux {
461 pinctrl_fec0_phy_int: pinctrl-fec0-phy-int {