Lines Matching +full:sck +full:- +full:gpios
1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
7 /dts-v1/;
15 stdout-path = &uart1;
23 audio_ext: oscillator-audio {
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <24576000>;
29 enet_ext: oscillator-ethernet {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
36 compatible = "gpio-leds";
37 pinctrl-names = "default";
38 pinctrl-0 = <&pinctrl_gpio_leds>;
41 led0: led-heartbeat {
43 gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>;
44 default-state = "on";
45 linux,default-trigger = "heartbeat";
49 reg_3p3v: regulator-3p3v {
50 compatible = "regulator-fixed";
51 regulator-name = "3P3V";
52 regulator-min-microvolt = <3300000>;
53 regulator-max-microvolt = <3300000>;
54 regulator-always-on;
57 reg_vcc_3v3_mcu: regulator-vcc3v3mcu {
58 compatible = "regulator-fixed";
59 regulator-name = "vcc_3v3_mcu";
60 regulator-min-microvolt = <3300000>;
61 regulator-max-microvolt = <3300000>;
65 compatible = "spi-gpio";
66 pinctrl-0 = <&pinctrl_gpio_spi>;
67 pinctrl-names = "default";
68 #address-cells = <1>;
69 #size-cells = <0>;
70 /* PTD12 ->RPIO[91] */
71 sck-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>;
72 /* PTD10 ->RPIO[89] */
73 miso-gpios = <&gpio2 25 GPIO_ACTIVE_HIGH>;
74 num-chipselects = <0>;
77 compatible = "pisosr-gpio";
79 gpio-controller;
80 #gpio-cells = <2>;
81 /* PTB18 -> RGPIO[40] */
82 load-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
83 spi-max-frequency = <100000>;
89 vref-supply = <®_vcc_3v3_mcu>;
94 vref-supply = <®_vcc_3v3_mcu>;
99 pinctrl-names = "default";
100 pinctrl-0 = <&pinctrl_can0>;
105 pinctrl-names = "default";
106 pinctrl-0 = <&pinctrl_can1>;
112 clock-names = "sxosc", "fxosc", "enet_ext", "audio_ext";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_dspi0>;
118 bus-num = <0>;
123 spi-max-frequency = <30000000>;
125 fsl,spi-cs-sck-delay = <200>;
126 fsl,spi-sck-cs-delay = <400>;
131 pinctrl-names = "default";
132 pinctrl-0 = <&pinctrl_dspi3>;
133 bus-num = <3>;
135 spi-slave;
136 #address-cells = <0>;
140 spi-max-frequency = <30000000>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_esdhc1>;
155 bus-width = <4>;
156 cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>;
161 phy-mode = "rmii";
162 phy-handle = <ðphy0>;
163 pinctrl-names = "default";
164 pinctrl-0 = <&pinctrl_fec0>;
168 #address-cells = <1>;
169 #size-cells = <0>;
171 ethphy0: ethernet-phy@1 {
174 clock-names = "rmii-ref";
180 phy-mode = "rmii";
181 phy-handle = <ðphy1>;
182 pinctrl-names = "default";
183 pinctrl-0 = <&pinctrl_fec1>;
187 #address-cells = <1>;
188 #size-cells = <0>;
190 ethphy1: ethernet-phy@1 {
193 clock-names = "rmii-ref";
199 clock-frequency = <400000>;
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_i2c2>;
216 assigned-clocks = <&clks VF610_CLK_NFC>;
217 assigned-clock-rates = <33000000>;
218 pinctrl-names = "default";
219 pinctrl-0 = <&pinctrl_nfc>;
223 compatible = "fsl,vf610-nfc-nandcs";
225 #address-cells = <1>;
226 #size-cells = <1>;
227 nand-bus-width = <16>;
228 nand-ecc-mode = "hw";
229 nand-ecc-strength = <24>;
230 nand-ecc-step-size = <2048>;
231 nand-on-flash-bbt;
236 pinctrl-names = "default";
237 pinctrl-0 = <&pinctrl_qspi0>;
241 compatible = "n25q128a13", "jedec,spi-nor";
242 #address-cells = <1>;
243 #size-cells = <1>;
244 spi-max-frequency = <66000000>;
245 spi-rx-bus-width = <4>;
250 compatible = "n25q128a13", "jedec,spi-nor";
251 #address-cells = <1>;
252 #size-cells = <1>;
253 spi-max-frequency = <66000000>;
254 spi-rx-bus-width = <2>;
260 pinctrl-names = "default";
261 pinctrl-0 = <&pinctrl_uart0>;
262 /delete-property/dma-names;
267 pinctrl-names = "default";
268 pinctrl-0 = <&pinctrl_uart1>;
269 /delete-property/dma-names;
274 pinctrl-names = "default";
275 pinctrl-0 = <&pinctrl_uart2>;
276 /delete-property/dma-names;
281 pinctrl-names = "default";
282 pinctrl-0 = <&pinctrl_uart3>;
283 /delete-property/dma-names;
288 disable-over-current;
293 disable-over-current;
314 pinctrl-names = "default";
315 pinctrl-0 = <&pinctrl_hog>;
461 pinctrl_gpio_spi: pinctrl-gpio-spi {