Lines Matching +full:0 +full:x5b
18 reg = <0x80000000 0x20000000>;
23 pinctrl-0 = <&pinctrl_gpio>;
39 pinctrl-0 = <&pinctrl_brcm_reg>;
49 pinctrl-0 = <&pinctrl_bt_reg>;
94 pinctrl-0 = <&pinctrl_i2c1>;
99 reg = <0x08>;
193 pinctrl-0 = <&pinctrl_i2c2>;
199 pinctrl-0 = <&pinctrl_ov2680>;
200 reg = <0x36>;
211 clock-lanes = <0>;
221 pinctrl-0 = <&pinctrl_i2c3>;
228 pinctrl-0 = <&pinctrl_i2c4>;
232 #sound-dai-cells = <0>;
233 reg = <0x0a>;
237 pinctrl-0 = <&pinctrl_sai1_mclk>;
245 reg = <0x60>;
254 port@0 {
255 reg = <0>;
267 pinctrl-0 = <&pinctrl_sai1>;
271 assigned-clock-rates = <0>, <36864000>;
277 pinctrl-0 = <&pinctrl_uart1>;
285 pinctrl-0 = <&pinctrl_uart3>;
294 pinctrl-0 = <&pinctrl_uart6>;
308 pinctrl-0 = <&pinctrl_usdhc1>;
319 pinctrl-0 = <&pinctrl_usdhc3>;
337 pinctrl-0 = <&pinctrl_wdog>;
345 MX7D_PAD_SD2_WP__GPIO5_IO10 0x14 /* WL_REG_ON */
351 MX7D_PAD_SD2_DATA3__GPIO5_IO17 0x14 /* BT_REG_ON */
357 MX7D_PAD_ENET1_RGMII_RD1__GPIO7_IO1 0x14
363 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
364 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
370 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f
371 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f
377 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f
378 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f
384 MX7D_PAD_I2C4_SCL__I2C4_SCL 0x4000007f
385 MX7D_PAD_I2C4_SDA__I2C4_SDA 0x4000007f
391 MX7D_PAD_LPSR_GPIO1_IO03__GPIO1_IO3 0x14
397 MX7D_PAD_SAI1_RX_DATA__SAI1_RX_DATA0 0x1f
398 MX7D_PAD_SAI1_TX_BCLK__SAI1_TX_BCLK 0x1f
399 MX7D_PAD_SAI1_TX_SYNC__SAI1_TX_SYNC 0x1f
400 MX7D_PAD_SAI1_TX_DATA__SAI1_TX_DATA0 0x30
406 MX7D_PAD_SAI1_MCLK__SAI1_MCLK 0x1f
412 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79
413 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79
419 MX7D_PAD_UART3_TX_DATA__UART3_DCE_TX 0x79
420 MX7D_PAD_UART3_RX_DATA__UART3_DCE_RX 0x79
421 MX7D_PAD_UART3_CTS_B__UART3_DCE_CTS 0x79
422 MX7D_PAD_UART3_RTS_B__UART3_DCE_RTS 0x79
428 MX7D_PAD_ECSPI1_MOSI__UART6_DTE_RX 0x79
429 MX7D_PAD_ECSPI1_SCLK__UART6_DTE_TX 0x79
435 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
436 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
437 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
438 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
439 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
440 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
441 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14 /* WL_HOST_WAKE */
447 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
448 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
449 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
450 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
451 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
452 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
453 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
454 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
455 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
456 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
457 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x19
463 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
464 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a
465 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
466 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
467 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
468 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
469 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
470 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
471 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
472 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
473 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1a
479 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
480 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b
481 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
482 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
483 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
484 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
485 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
486 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
487 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
488 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
489 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x1b
497 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74