Lines Matching +full:0 +full:x59
24 pinctrl-0 = <&pinctrl_leds_debug>;
41 pinctrl-0 = <&pinctrl_ecspi1>;
45 flash@0 {
48 reg = <0>;
56 pinctrl-0 = <&pinctrl_enet1>;
60 assigned-clock-rates = <0>, <100000000>;
67 #size-cells = <0>;
69 fec1_phy: ethernet-phy@0 {
71 pinctrl-0 = <&pinctrl_enet1_phy_reset>,
73 reg = <0>;
84 pinctrl-0 = <&pinctrl_i2c1>;
89 reg = <0x08>;
179 reg = <0x50>;
184 reg = <0x52>;
194 pinctrl-0 = <&pinctrl_uart2>;
202 pinctrl-0 = <&pinctrl_uart4>;
219 reg = <0xa3 0x4000>;
235 pinctrl-0 = <&pinctrl_usdhc1>;
245 pinctrl-0 = <&pinctrl_usdhc3>;
262 MX7D_PAD_ECSPI1_SCLK__ECSPI1_SCLK 0x2
263 MX7D_PAD_ECSPI1_MOSI__ECSPI1_MOSI 0x2
264 MX7D_PAD_ECSPI1_MISO__ECSPI1_MISO 0x2
265 MX7D_PAD_ECSPI1_SS0__GPIO4_IO19 0x59
271 MX7D_PAD_SD2_CD_B__ENET1_MDIO 0x3
272 MX7D_PAD_SD2_WP__ENET1_MDC 0x3
273 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1
274 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1
275 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1
276 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1
277 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1
278 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1
279 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1
280 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1
281 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1
282 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1
283 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1
284 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1
290 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x14
297 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f
298 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f
304 MX7D_PAD_EPDC_DATA08__GPIO2_IO8 0x59
311 MX7D_PAD_UART2_RX_DATA__UART2_DCE_RX 0x79
312 MX7D_PAD_UART2_TX_DATA__UART2_DCE_TX 0x79
318 MX7D_PAD_SD2_DATA0__UART4_DCE_RX 0x79
319 MX7D_PAD_SD2_DATA1__UART4_DCE_TX 0x79
325 MX7D_PAD_SD1_CMD__SD1_CMD 0x59
326 MX7D_PAD_SD1_CLK__SD1_CLK 0x19
327 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59
328 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59
329 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59
330 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59
336 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
337 MX7D_PAD_SD3_CLK__SD3_CLK 0x19
338 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
339 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
340 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
341 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
342 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
343 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
344 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
345 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
346 MX7D_PAD_SD3_RESET_B__SD3_RESET_B 0x59
354 MX7D_PAD_LPSR_GPIO1_IO02__GPIO1_IO2 0x08