Lines Matching +full:0 +full:x5b
14 reg = <0x80000000 0x20000000>;
34 pinctrl-0 = <&pinctrl_i2c1>;
40 pinctrl-0 = <&pinctrl_pmic1>;
42 reg = <0x08>;
134 reg = <0x1e>;
141 reg = <0x50>;
148 reg = <0x56>;
155 reg = <0x68>;
162 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x40000078
163 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x40000078
169 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x4000005C
175 MX7D_PAD_EPDC_DATA00__QSPI_A_DATA0 0x5A
176 MX7D_PAD_EPDC_DATA01__QSPI_A_DATA1 0x5A
177 MX7D_PAD_EPDC_DATA02__QSPI_A_DATA2 0x5A
178 MX7D_PAD_EPDC_DATA03__QSPI_A_DATA3 0x5A
179 MX7D_PAD_EPDC_DATA05__QSPI_A_SCLK 0x11
180 MX7D_PAD_EPDC_DATA06__QSPI_A_SS0_B 0x54
181 MX7D_PAD_EPDC_DATA07__QSPI_A_SS1_B 0x54
188 MX7D_PAD_EPDC_DATA04__GPIO2_IO4 0x52
194 MX7D_PAD_SD3_CMD__SD3_CMD 0x59
195 MX7D_PAD_SD3_CLK__SD3_CLK 0x56
196 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59
197 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59
198 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59
199 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59
200 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59
201 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59
202 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59
203 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59
204 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19
210 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a
211 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
212 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a
213 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a
214 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a
215 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a
216 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a
217 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a
218 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a
219 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a
220 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a
226 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b
227 MX7D_PAD_SD3_CLK__SD3_CLK 0x51
228 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b
229 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b
230 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b
231 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b
232 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b
233 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b
234 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b
235 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b
236 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b
244 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x30
251 pinctrl-0 = <&pinctrl_qspi &pinctrl_qspi_reset>;
254 flash0: flash@0 {
256 reg = <0>;
269 pinctrl-0 = <&pinctrl_usdhc3>;
283 pinctrl-0 = <&pinctrl_wdog1>;