Lines Matching +full:reset +full:- +full:gpios
1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Rabeeh Khoury <rabeeh@solid-run.com>, based on Russell King clearfog work
9 SERDES mapping -
10 0. SATA1 on CON18, or optionally mini PCIe CON3 - PCIe0
12 2. SATA0 on CON17, or optionally mini PCIe CON4 - PCIe1
14 4. mini PCIe CON2 - PCIe2
17 USB 2.0 mapping -
18 0. USB 2.0 - 0 USB pins header CON12
19 1. USB 2.0 - 1 mini PCIe CON2
20 2. USB 2.0 - 2 to USB 3.0 connector (used with SERDES #3)
22 Pin mapping -
23 0,1 - console UART
24 2,3 - I2C0 - connected to I2C EEPROM, two temperature sensors,
26 4,5 - MDC/MDIO
27 6..17 - RGMII
28 18 - Topaz switch reset (active low)
29 19 - 1512 phy reset
30 20 - 1512 phy reset (eth2, optional)
31 21,28,37,38,39,40 - SD0
32 22 - USB 3.0 current limiter enable (active high)
33 24 - SFP TX fault (input active high)
34 25 - SFP present (input active low)
35 26,27 - I2C1 - connected to SFP
36 29 - Fan PWM
37 30 - CON4 mini PCIe wifi disable
38 31 - CON3 mini PCIe wifi disable
39 32 - Fuse programming power toggle (1.8v)
40 33 - CON4 mini PCIe reset
41 34 - CON2 mini PCIe wifi disable
42 35 - CON3 mini PCIe reset
43 36 - Rear button (GPIO active low)
44 41 - CON1 front panel connector
45 42 - Front LED1, or front panel CON1
46 43 - Micron L-PBGA 24 ball SPI (1Gb) CS, or TPM SPI CS
47 44 - CON2 mini PCIe reset
48 45 - TPM PIRQ signal, or front panel CON1
49 46 - SFP TX disable
50 47 - Control isolation of boot sensitive SAR signals
51 48 - PSE reset
52 49 - PSE OSS signal
53 50 - PSE interrupt
54 52 - Front LED2, or front panel
55 53 - Front button
56 54 - SFP LOS (input active high)
57 55 - Fan sense
58 56(mosi),57(clk),58(miso) - SPI interface - 32Mb SPI, 1Gb SPI and TPM
59 59 - SPI 32Mb W25Q32BVZPIG CS0 chip select (bootable)
62 /dts-v1/;
63 #include <dt-bindings/input/input.h>
64 #include <dt-bindings/gpio/gpio.h>
65 #include <dt-bindings/leds/common.h>
66 #include "armada-385.dtsi"
72 /* So that mvebu u-boot can update the MAC addresses */
81 stdout-path = "serial0:115200n8";
89 reg_3p3v: regulator-3p3v {
90 compatible = "regulator-fixed";
91 regulator-name = "3P3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
97 reg_5p0v: regulator-5p0v {
98 compatible = "regulator-fixed";
99 regulator-name = "5P0V";
100 regulator-min-microvolt = <5000000>;
101 regulator-max-microvolt = <5000000>;
102 regulator-always-on;
105 v_usb3_con: regulator-v-usb3-con {
106 compatible = "regulator-fixed";
108 pinctrl-names = "default";
109 pinctrl-0 = <&cf_gtr_usb3_con_vbus>;
110 regulator-max-microvolt = <5000000>;
111 regulator-min-microvolt = <5000000>;
112 regulator-name = "v_usb3_con";
113 vin-supply = <®_5p0v>;
114 regulator-boot-on;
115 regulator-always-on;
125 internal-regs {
132 pinctrl-0 = <&i2c0_pins>;
133 pinctrl-names = "default";
138 pinctrl-0 = <&cf_gtr_i2c1_pins>;
139 pinctrl-names = "default";
144 cf_gtr_switch_reset_pins: cf-gtr-switch-reset-pins {
149 cf_gtr_usb3_con_vbus: cf-gtr-usb3-con-vbus {
154 cf_gtr_fan_pwm: cf-gtr-fan-pwm {
159 cf_gtr_i2c1_pins: i2c1-pins {
165 cf_gtr_sdhci_pins: cf-gtr-sdhci-pins {
172 cf_gtr_isolation_pins: cf-gtr-isolation-pins {
177 cf_gtr_poe_reset_pins: cf-gtr-poe-reset-pins {
182 cf_gtr_spi1_cs_pins: spi1-cs-pins {
187 cf_gtr_front_button_pins: cf-gtr-front-button-pins {
192 cf_gtr_rear_button_pins: cf-gtr-rear-button-pins {
199 bus-width = <4>;
200 no-1-8-v;
201 non-removable;
202 pinctrl-0 = <&cf_gtr_sdhci_pins>;
203 pinctrl-names = "default";
206 wp-inverted;
218 vbus-supply = <&v_usb3_con>;
227 * the mini-PCIe connectors on the board.
230 reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
235 reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>;
240 reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
248 i2c-bus = <&i2c1>;
249 los-gpio = <&gpio1 22 GPIO_ACTIVE_HIGH>;
250 mod-def0-gpio = <&gpio0 25 GPIO_ACTIVE_LOW>;
251 tx-disable-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
254 gpio-keys {
255 compatible = "gpio-keys";
256 pinctrl-0 = <&cf_gtr_rear_button_pins &cf_gtr_front_button_pins>;
257 pinctrl-names = "default";
259 button-0 {
261 gpios = <&gpio1 4 GPIO_ACTIVE_LOW>;
262 linux,can-disable;
266 button-1 {
268 gpios = <&gpio1 21 GPIO_ACTIVE_LOW>;
269 linux,can-disable;
274 gpio-leds {
275 compatible = "gpio-leds";
280 gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
286 gpios = <&gpio1 20 GPIO_ACTIVE_HIGH>;
301 pinctrl-0 = <&ge0_rgmii_pins>;
302 pinctrl-names = "default";
304 phy-mode = "rgmii-id";
305 buffer-manager = <&bm>;
306 bm,pool-long = <0>;
307 bm,pool-short = <1>;
313 bm,pool-long = <2>;
314 bm,pool-short = <1>;
315 buffer-manager = <&bm>;
317 phy-mode = "2500base-x";
320 fixed-link {
322 full-duplex;
328 bm,pool-long = <3>;
329 bm,pool-short = <1>;
330 buffer-manager = <&bm>;
331 managed = "in-band-status";
333 phy-mode = "sgmii";
339 pinctrl-names = "default";
340 pinctrl-0 = <&mdio_pins>;
343 phy_dedicated: ethernet-phy@0 {
346 * register, rather than preserving reset-loaded setting.
349 marvell,reg-init = <3 16 0 0x1017>;
355 pinctrl-0 = <&uart0_pins>;
356 pinctrl-names = "default";
364 pinctrl-0 = <&spi1_pins &cf_gtr_spi1_cs_pins>;
365 pinctrl-names = "default";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 compatible = "w25q32", "jedec,spi-nor";
373 spi-max-frequency = <3000000>;
379 pinctrl-0 = <&i2c0_pins>;
380 pinctrl-names = "default";
411 pinctrl-0 = <&cf_gtr_fan_pwm>;
412 pinctrl-names = "default";
414 wifi-disable {
415 gpio-hog;
416 gpios = <30 GPIO_ACTIVE_LOW>, <31 GPIO_ACTIVE_LOW>;
417 output-low;
418 line-name = "wifi-disable";
423 pinctrl-0 = <&cf_gtr_isolation_pins &cf_gtr_poe_reset_pins>;
424 pinctrl-names = "default";
426 lte-disable {
427 gpio-hog;
428 gpios = <2 GPIO_ACTIVE_LOW>;
429 output-low;
430 line-name = "lte-disable";
434 * This signal, when asserted, isolates Armada 38x sample at reset pins
435 * from control of external devices. Should be de-asserted after reset.
437 sar-isolation {
438 gpio-hog;
439 gpios = <15 GPIO_ACTIVE_LOW>;
440 output-low;
441 line-name = "sar-isolation";
444 poe-reset {
445 gpio-hog;
446 gpios = <16 GPIO_ACTIVE_LOW>;
447 output-low;
448 line-name = "poe-reset";