Lines Matching +full:- +full:- +full:- +full:-
1 .. SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
5 HDAudio multi-link extensions on Intel platforms
10 This file documents the 'multi-link structure' introduced in 2015 with
20 LCAP.ALT=0x0 - since the ALT bit was previously reserved, this is a
21 backwards-compatible change.
28 ----------------------------------
32 +-----------+
34 +-----------+
35 | ML cap #1 |---+
36 +-----------+ |
38 +--> 0x0 +---------------+ LCAP
40 +---------------+
42 +---------------+
44 +---------------+
46 +---------------+
48 +---------------+
50 +---------------+
52 +---------------+
54 0x4 +---------------+ LCTL
56 +---------------+
58 +---------------+
60 +---------------+
62 +---------------+
64 0x8 +---------------+ LOSIDV
66 +---------------+
68 +---------------+
70 +---------------+
72 0xC +---------------+ LSDIID
74 +---------------+
76 +---------------+
78 +---------------+
91 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
92 - number of sublinks (manager IP) in LCAP.LSCOUNT
93 - power management moved from SHIM to LCTL.SPA bits
94 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
95 - mapping of SoundWire codecs to SDI ID bits
96 - move of SHIM and Cadence registers to different offsets, with no
101 --------------------------------------------------------
105 +-----------+
107 +-----------+
109 +-----------+
110 | ML cap #2 |---+
111 +-----------+ |
113 +--> 0x0 +---------------+ LCAP
115 +---------------+
117 +---------------+
119 +---------------+
121 +---------------+
122 | SLCOUNT=4 |-----------+
123 +---------------+ |
125 0x4 +---------------+ LCTL |
127 +---------------+ |
129 +---------------+ |
131 +---------------+ for each sublink x
133 +---------------+ |
135 +---------------+ |
137 0x8 +---------------+ LOSIDV |
139 +---------------+ |
141 +---------------+ |
142 … | L1OSIDV1 | +---+----------------------------------------------------------+
143 … +---------------+ | |
145 …0xC + 0x2 * x +---------------+ LSDIIDx +---> 0x30000 +-----------------+ 0x00030000 …
147 … +---------------+ | | generic | |
148 … | SDIID... | | +-----------------+ 0x00030100 |
149 … +---------------+ | | SoundWire IP | |
150 … | SDIID0 | | +-----------------+ 0x00036000 |
151 … +---------------+ | | SoundWire SHIM | |
152 … | | vendor-specific | |
153 … 0x1C +---------------+ LSYNC | +-----------------+ |
155 … +---------------+ | +-----------------+ 0x00030000 + 0x8000 * x
157 +---------------+ | | generic |
158 … | SYNCPU | | +-----------------+ 0x00030100 + 0x8000 * x
159 +---------------+ | | SoundWire IP |
160 … | SYNPRD | | +-----------------+ 0x00036000 + 0x8000 * x
161 +---------------+ | | SoundWire SHIM |
162 | | vendor-specific |
163 0x20 +---------------+ LEPTR | +-----------------+
165 +---------------+ |
167 +---------------+ |
168 | PTR |------------+
169 +---------------+
183 - multi-link synchronization: capabilities in LCAP.LSS and control in LSYNC
184 - power management with LCTL.SPA bits
185 - hand-over to the DSP for access to multi-link registers, SHIM/IP with LCTL.OFLEN
187 - move of DMIC registers to different offsets, with no change in
192 ---------------------------
196 +-----------+
198 +-----------+
200 +-----------+
201 | ML cap #2 |---+
202 +-----------+ |
204 +--> 0x0 +---------------+ LCAP
206 +---------------+
208 +---------------+
210 +---------------+
212 +---------------+
214 0x4 +---------------+ LCTL
216 +---------------+
218 +---------------+
220 +---------------+
222 +---------------+
224 … +---------------+ +---> 0x10000 +-----------------+ 0x00010000
226 0x8 +---------------+ LOSIDV | | generic |
227 … | L1OSIVD15 | | +-----------------+ 0x00010100
228 +---------------+ | | DMIC IP |
229 … | L1OSIDV.. | | +-----------------+ 0x00016000
230 +---------------+ | | DMIC SHIM |
231 | L1OSIDV1 | | | vendor-specific |
232 +---------------+ | +-----------------+
234 0x20 +---------------+ LEPTR |
236 +---------------+ |
238 +---------------+ |
239 | PTR |-----------+
240 +---------------+
253 - number of sublinks (SSP IP instances) in LCAP.LSCOUNT
254 - power management moved from SHIM to LCTL.SPA bits
255 - hand-over to the DSP for access to multi-link registers, SHIM/IP
257 - move of SHIM and SSP IP registers to different offsets, with no
262 -----------------------------------------------------------
266 +-----------+
268 +-----------+
270 +-----------+
271 | ML cap #2 |---+
272 +-----------+ |
274 +--> 0x0 +---------------+ LCAP
276 +---------------+
278 +---------------+
280 +---------------+
281 … | SLCOUNT=3 |-------------------------for each sublink x -------------------------+
282 … +---------------+ |
284 … 0x4 +---------------+ LCTL |
286 … +---------------+ |
288 … +---------------+ |
290 … +---------------+ |
292 … +---------------+ |
294 … +---------------+ +---> 0x28000 +-----------------+ 0x00028000 |
296 … 0x8 +---------------+ LOSIDV | | generic | |
297 … | L1OSIVD15 | | +-----------------+ 0x00028100 |
298 … +---------------+ | | SSP IP | |
299 … | L1OSIDV.. | | +-----------------+ 0x00028C00 |
300 … +---------------+ | | SSP SHIM | |
301 … | L1OSIDV1 | | | vendor-specific | |
302 … +---------------+ | +-----------------+ |
304 … 0x20 +---------------+ LEPTR | +-----------------+ 0x00028000 + 0x1000 * x
306 +---------------+ | | generic |
307 … | VER | | +-----------------+ 0x00028100 + 0x1000 * x
308 +---------------+ | | SSP IP |
309 … | PTR |-----------+ +-----------------+ 0x00028C00 + 0x1000 * x
310 +---------------+ | SSP SHIM |
311 | vendor-specific |
312 +-----------------+